Serial flash semiconductor memory

A flash memory comprising:

• a flash memory array;
• and
• an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol;
• wherein a first one of the pins is configurable with the interface circuit as a data output pin in compliance with the single-bit serial protocol during an output sequence of a “Fast Read” instruction;
• wherein the first pin and a second one of the pins are configurable with the interface circuit as data output pins in compliance with the multiple-bit serial protocol during an output sequence of a “Fast Read Dual Output” instruction;
• and
• wherein the second pin is configurable with the interface circuit as a data input pin in compliance with the single-bit serial protocol during respective input sequences of the “Fast Read” instruction and the “Fast Read Dual Output” instruction.

A flash memory comprising:

• a flash memory array;
• and
• an interface circuit coupled to the flash memory array, the interface circuit having a clock pin, a chip select pin, and first, second, third and fourth pins, and being selectively compliant with Serial Peripheral Interface protocol and a four-bit serial protocol;
• wherein the first pin is configurable with the interface circuit as a data output pin and the second pin is configurable with the interface circuit as an input pin for single-bit serial transfer in compliance with the Serial Peripheral Interface protocol;
• and
• wherein the first, second, third and fourth pins are further configurable with the interface circuit as input/output pins for four-bit serial transfers that are addressable but unassociated with dedicated address pins in compliance with the four-bit serial protocol.

A flash memory comprising:

• a flash memory array;
• and
• an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol;
• wherein a first one of the pins is selectively configurable with the interface circuit as an input in compliance with the single bit serial protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol;
• and
• wherein a second one of the pins is selectively configurable with the interface circuit as a data output in compliance with the single bit serial protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol.

A flash memory comprising:

• a flash memory array;
• and
• an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol;
• wherein a first one of the pins is configurable with the interface circuit for single-bit serial input in compliance with the single-bit serial protocol;
• wherein a second one of the pins is configurable with the interface circuit for single-bit serial data output in compliance with the single-bit serial protocol;
• and
• wherein the first pin and the second pin are configurable with the interface circuit for multiple-bit serial output that is addressable but unassociated with dedicated address pins in compliance with the multiple-bit serial protocol.

A packaged flash memory device comprising:

• an only eight-contact SOIC or MLP package body;
• a flash memory array contained in the package body;
• an interface circuit contained in the package body and coupled to the flash memory array, the interface circuit being selectively compliant with a Serial Peripheral Interface protocol and an Enhanced Serial Peripheral Interface protocol;
• and
• four or fewer data contacts, a clock contact, and a chip select contact mounted on the package body and coupled to the interface circuit, a first one of the data contacts being selectively configurable with the interface circuit as an input in compliance with the Serial Peripheral Interface protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the Enhanced Serial Peripheral Interface protocol, and a second one of the data contacts being selectively configurable with the interface circuit as a data output in compliance with the Serial Peripheral Interface protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the Enhanced Serial Peripheral Interface protocol.

A packaged flash memory device operable under either a single-bit serial protocol or a multiple-bit serial protocol, comprising:

• an only eight-contact SOIC or MLP package body;
• first and second data contacts, a clock contact, and a chip select contact mounted on the package body;
• a flash memory array contained in the package body;
• and
• an interface circuit contained in the package body and coupled to the flash memory array and to the first and second data contacts, a clock contact, and a chip select contact, the interface circuit being operable under a single-bit serial protocol to establish the first data contact as an input and the second data contact as a data output, and operable under a multiple-bit serial protocol to establish the first and second data contacts as inputs/outputs that are addressable but unassociated with dedicated address pins.

A packaged flash memory device operable under either a single-bit serial protocol or a multiple-bit serial protocol, comprising:

• an SOIC or MLP package body;
• a flash memory array contained in the package body;
• an interface circuit contained in the package body and coupled to the flash memory;
• a clock contact coupled to the interface circuit;
• a chip select contact coupled to the interface circuit;
• and
• first and second data contacts coupled to the interface circuit, the interface circuit being operable under a single-bit serial protocol to establish the first data contact as an input and the second data contact as a data output, and operable under a multiple-bit serial protocol to establish the first and second data contacts as data outputs that are addressable but unassociated with dedicated address pins.