Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies
AssigneesSarnoff Corporation, Sarnoff Europe BVBA
InventorsMarkus Paul Josef Mergens, Cornelius Christian Russ, John Armer, Koen Gerard Maria Verhaege
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Abstract
An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry is provided herein. In one embodiment, a circuit for protecting an integrated circuit from ESD includes a protected circuit node in the integrated circuit, a multiple stage transistor pump circuit coupled to the protected circuit node, and an electrostatic discharge protection circuit having a trigger coupled to the multiple stage transistor pump circuit. The multiple stage transistor pump circuit may comprise a Darlington transistor pump circuit.
Claims5
A circuit for protecting an integrated circuit from electrostatic discharge, comprising:
- a protected circuit node in the integrated circuit;
- a silicon controlled rectifier in electrical communication with the protected circuit node and a ground, the silicon controlled rectifier having first and second trigger gates, wherein said first trigger gate comprise a base of a npn transistor and second trigger gate comprise a base of a pnp transistor;
- and
- a plurality of serially-coupled trigger diodes having first and second ends in electrical communication with the first and second trigger gates, respectively, wherein each of the plurality of serially-coupled trigger diodes is biased in a forward conduction direction from the second trigger gate to the first trigger gate.
Dependencies are inferred from the claim text.