Vertical gate-depleted single electron transistor

Abstract

A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative. The depletion region expands toward the center of the device and forms a lateral confinement to the quantum well, wherein a quantum dot is obtained. Because the size of the quantum dot is so small, the Coulomb charging energy achieved is large enough to let the device operate at room temperature.

Dependencies are inferred from the claim text.