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US 7,547,597 B2Granted
Direct alignment scheme between multiple lithography layers
AssigneeIntel Corporation
InventorsDerchang Kau, Khaled Hasnat, Everett Lee
Life of this patent
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Abstract
A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
Claims19
A method comprising:
- forming a first layer on a substrate;
- patterning the first layer to include a wordline of a memory cell;
- forming a second layer on the substrate;
- patterning the second layer to include logic circuitry having a gate;
- and
- passing a contact via through at least one of the first layer and the second layer and at least into the other of the first layer and second layer, the contact via being positioned adjacent the wordline in the first patterned layer and the gate in the second patterned layer,
- wherein a smallest lateral spacing between the contact via and the adjacent wordline in the first layer is smaller than the nesting tolerance of an indirect alignment scheme, and
- wherein a smallest lateral spacing between the contact via and the adjacent gate in the second layer is smaller than the nesting tolerance of an indirect alignment scheme.
5 more elements
A method comprising:
- forming a diffusion layer on a substrate:
- forming a first layer on a substrate;
- patterning the first layer to include a collection of wordlines of one or more memory cells, wherein patterning the first layer comprises forming a first masking layer directly aligned to the diffusion layer and etching the first layer;
- forming a second layer on the substrate;
- patterning the second layer to include logic circuitry having a collection of gates that are perpendicular to the collection of wordlines of the one or more memory cells, wherein patterning the second layer comprises forming a second masking layer directly aligned to the first masking layer and etching the second layer;
- forming a dielectric layer on the substrate;
- and
- patterning the dielectric layer to include a contact via to provide electrical contact to the substrate, wherein patterning the dielectric layer comprises
- forming a third masking layer directly aligned to the first masking layer in a first direction and directly aligned to the second masking layer in a second direction, and
- using openings in the third masking layer to form a plurality of bitline contacts.
7 more elements
Dependencies are inferred from the claim text.