US 7,547,589 B2Granted

Method for fabricating semiconductor device, and electro-optical device, integrated circuit and electronic apparatus including the semiconductor device

AssigneeSeiko Epson Corporation

InventorChiharu Iriguchi

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Abstract

The invention provides a technique that enables formation of minute patterns on an uneven substrate in volume production without reducing productivity. The method for fabricating a semiconductor device includes: first patterning a semiconductor film on a substrate to form element regions, each of which will be provided with a source/drain region and a channel region, second forming a gate insulating film covering segments of the patterned semiconductor film in the respective element regions, third forming gate electrodes on the gate insulating film at predetermined positions, and fourth forming the source/drain region and the channel region in each element region. At least the gate electrodes are formed by a process including an exposure step through a holographic exposure mask in the third step, and by a process including an exposure step through a projection exposure mask, the element regions are formed in the first step, and the source/drain regions and the channel regions are formed in the fourth step.

Claims17

Dependent claims

A method for fabricating a semiconductor device including transistors, each having a gate electrode, a source/drain region, and a channel region on a substrate, the method comprising:

first, patterning a semiconductor film on the substrate to form element regions, each to be provided with the source/drain region and the channel region, the first patterning step including:
forming a second photosensitive film on the semiconductor film using a photosensitive material,
exposing the second photosensitive film through a first projection exposure mask using a stepper or a scanner, the first projection exposure mask having an exposure pattern corresponding to the element regions and an exposure pattern corresponding to a first alignment mark used for alignment of a holographic exposure mask,
developing the exposed second photosensitive film and removing the second photosensitive film excluding areas corresponding to the element regions and an area corresponding to the first alignment mark, and
etching the conductive film through the second photosensitive film, as a mask, remaining on the semiconductor film to form the element regions and the first alignment mark;
second, forming a gate insulating film covering segments of the patterned semiconductor film in the respective element regions;
third, forming the gate electrodes on the gate insulating film at predetermined positions;
and
fourth, forming the source/drain region and the channel region in each of the element regions, the gate electrodes being formed by a process including an exposure step through the holographic exposure mask in the third step and the source/drain regions and the channel regions being formed by a process including an exposure step through a projection exposure mask using a stepper or a scanner in the fourth step.

6 more elements

A method of fabricating a semiconductor device, comprising:

forming a semiconductor film over a substrate;
forming a first photosensitive film over the semiconductor film;
exposing the first photosensitive film through a first projection exposure mask having a first exposure pattern corresponding to an element region and a first alignment mark;
forming the element region and the first alignment mark by patterning the semiconductor film;
forming an insulating film over the element region;
forming a conductive film over the insulating film;
forming a second photosensitive film over the conductive film;
exposing the second photosensitive film through a holographic exposure mask having a second exposure pattern corresponding to an electrode, the holographic exposure mask being aligned with the first alignment mark;
forming the electrode over the insulating film by patterning the conductive film;
and
forming a source/drain region and a channel region in the element region, the source/drain region and the channel region being formed by a process including an exposure step through a projection exposure mask using a stepper or a scanner.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/840,297Filed 7 May 2004
Priority: JP 2003-13740515 May 2003
Published: US 2005/0026340 A13 Feb 2005
Granted: 16 Jun 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks
H10D 86/40
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10D
Inorganic electric semiconductor devices