Defect identification system and method for repairing killer defects in semiconductor devices

#The present invention is directed, in general, to semiconductor fabrication and, more specifically, to an in-line defect identification system and method for repairing killer defects in semiconductor devices upon detection.

#In the realm of semiconductor fabrication, systems and methods for maximizing chip yield are critical to the success of a semiconductor manufacturing company. Higher yields allows companies to distribute the manufacturing costs over a greater quantity of products, thereby reducing the sales price or increasing the profit margin.

#Optical, laser-based and SEM inspection tools are key pieces of equipment for yield maintenance and improvement. They are used to inspect wafers for defects at numerous points in the production process. Their data is used for three fundamental purposes: statistical process control (SPC), identification and quantification of the defects limiting yield for process improvement purposes, and yield modeling.

#FIGS. 1A and 1B are schematic representations of a metal layer of a semiconductor device or die illustrating a shorting defect and its repair;

#FIGS. 2A and 2B are schematic representations of an open conductor defect in a metal layer and its repair;

#FIG. 3 is a flow chart representation of a process for defect analysis and repair; and

#The majority of the yield lost for integrated circuits is due to defects that are of sub-micron size, involve the shorting together of elements of a single mask level (such as metal or gate stack runners) or the creation of opens at the same levels, and which can be detected using in-line inspection tools. The shorting mechanisms include metal to metal shorts in either copper or aluminum technologies, gate-stack to gate-stack shorts, gate-stack to window shorts and active region to active region shorts. In-line inspection tools are capable of detecting and locating most of these shorted conditions. For example, U.S. Pat. No. 6,047,083 describes a method and apparatus for pattern inspection that can be used to identify killer defects on semiconductor dies. Most killer defects create a single short between two adjacent elements and therefore only need a minor repair to become non-yield limiting. However, the present invention contemplates that killer defects that cause shorts between more than two elements could be repaired by multiple-step corrective action.

#Referring now to FIG. 1A, there is shown a plan view of a small segment of a semiconductor die and, more particularly, a representation of a metal layer on a die such as, for example, metal 3. The metal layer includes a plurality of electrical conductors 12, 14 and 16. A defect 18, which may be characterized as a killer defect, short circuits conductor 12 to conductor 14. FIG. 2B shows the same die layer after repair of the killer defect by simply cutting through the defect 18 so that the electrical short between the conductor elements 12 and 14 has been eliminated.

#FIG. 2A illustrates another form of killer defect in a semiconductor die layer in which the electrical conductor 20 has an open or space so that continuity through the conductor element is lost. As shown in FIG. 2B, the open killer defect indicated at 22 can be repaired by creating an electrically conducting bridge between the spaced-apart ends of the conductor element 20.