Method for forming MRAM bit having a bottom sense layer utilizing electroless plating

#The present invention relates to a magnetic random access memory (MRAM) and a fabricating method thereof, and more particularly to a method of forming an MRAM cell having a bottom sense layer.

#Magnetic random access memories (MRAMs) employ memory cells having magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, in the form of relative magnetic orientations of spaced thin magnetic multilayer films forming each memory cell. Each MRAM cell has two stable magnetic film orientations, one which produces a high resistance across the cell representing e.g. a logic state 0 and another which produces a lower resistance across the cell representing e.g. a logic state 1, or vice versa.

#A typical multilayer-film MRAM array includes a number of bit or digit (column) lines intersected by a number of word (row) lines. An MRAM cell is formed between a digit and row line at each intersection.

#FIG. 1 is a schematic three-dimensional view of a portion of a conventional MRAM structure;

#FIG. 2 is a side sectional view of the MRAM structure of FIG. 1 showing a side conductive layer formed thereon;

#FIG. 3 illustrates a partial cross-sectional view of a semiconductor topography, at an intermediate stage of the processing, wherein a MRAM structure will be constructed in accordance with the present invention;

#In the following detailed description, reference is made to various exemplary embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention.

#The term “substrate” used in the following description may include any semiconductor-based structure that has a semiconductor surface. Structure must be understood to include silicon, silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could be silicon-germanium, germanium, or gallium arsenide. When reference is made to substrate in the following description, previous process steps may have been utilized to form regions or junctions in or on the base semiconductor or foundation.

#Referring now to the drawings, where like elements are designated by like reference numerals, FIGS. 3-19 illustrate an exemplary embodiment of a method of forming MRAM structures in accordance with the invention. FIG. 3 depicts a portion of a semiconductor substrate 50 on which underlying layer 52 has been already formed according to well-known methods of the prior art. The underlying layer 52 could include, for example, circuit layers forming CMOS devices and circuits. Next, an insulating layer 54 is formed over the substrate 50 and the underlying layer 52. In an exemplary embodiment of the invention, the insulating layer 54 is blanket deposited by spin coating to a thickness of about 1,000 Angstroms to about 10,000 Angstroms. However, other known deposition methods, such as sputtering by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or physical vapor deposition (PVD), may be used also in accordance with the characteristics of the IC device already formed. The insulating layer 54 may be formed of a conventional insulator, for example, BPSG, a thermal oxide of silicon, such as SiO or SiO2, or a nitride such as Si3N4. Alternatively, a high temperature polymer, such as a polyimide, or a low dielectric constant inorganic material may also be employed.