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US 7,538,368 B2Granted
Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics
AssigneePanasonic Corporation
InventorJunichi Yano
Life of this patent
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Abstract
In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.
Claims12
A standard cell having a rectangular shape defined by a first direction and a second direction that is perpendicular to the first direction, the standard cell comprising:
- a plurality of transistors each having a diffusion region and a gate,
- a power supply wiring extended in the first direction,
- wherein the plurality of transistors include:
- at least one first transistor having larger gate length than the other transistors;
- and
- at least one second transistor adjacent to the first transistor and having a diffusion region apart from a diffusion region of the first transistor, and
- wherein the gate length of the at least one first transistor is defined by a length of gate in the first direction, and
- wherein a dummy gate is provided between the first transistor and the second transistor,
- a source/drain of the first transistor and a source/drain of the second transistor are separated;
- a width of the dummy gate in the first direction is smaller than a distance between the source/drain of the first transistor and the source/drain of the second transistor;
- and
- the dummy gate is provided in a region between the first and second transistors when viewed in plan view.
9 more elements
Dependencies are inferred from the claim text.