Digital memory

A neural network memory configuration for use in a computer system, the memory comprising:

• a plurality of address decoder neurons each of which is connected to a predetermined number of input neurons;
• a data memory having a plurality data neurons, each of the said address decoder neurons being activatable to select some of the plurality of data neurons;
• the address decoder neurons including means to receive a signal representing a firing of an input neuron to which it is connected;
• and
• wherein an address decoder neuron comprises means to activate data neurons if firing signals are received from at least a predetermined minimum number of input neurons to which the address decoder neuron is connected.

A method for operating a memory for use in a computer system, the memory comprising:

• a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states;
• a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines;
• wherein an input address having a predetermined number of bits is input to the address decoder, the identifier of an address decoder is compared with the input address and address decoders are activated if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier;
• wherein each address decoder identifier has an equal number of bits set to the first selectable state;
• and
• wherein an input address has a predetermined number of bits set to the first selectable state.

A memory configuration for use in a computer system, the memory comprising:

• a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states;
• a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select a predetermined one of the plurality of word lines;
• the address decoders comprising means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address, and
• wherein the memory further comprises means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.

A method for operating a memory for use in a computer system, the method comprising:

• allocating to each of a plurality of address decoders an identifier having a predetermined number of bits, each bit having first and second selectable states;
• and
• activating each of said address decoders to select a predetermined one of a plurality of word lines in a data memory having a plurality of word lines of predetermined length,
• wherein an input address having a predetermined number of bits is input to the address decoder, the identifier of an address decoder is compared with the input address and address decoders are activated if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.

A memory configuration for use in a computer system, the memory comprising:

• a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states;
• and
• a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines;
• the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address;
• wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier;
• wherein the data memory comprises a plurality of single bit memories, such that each bit of each word line is stored in a single bit memory;
• and
• wherein the data memory comprises a data input line containing an equal number of bits to each of the plurality of word lines, the data input line being configured to receive input data containing a predetermined number of bits set to the first selectable state.