Semiconductor integrated circuit device
AssigneeElpida Memory, Inc.
InventorMinoru Yamagami
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.
Claims20
A semiconductor integrated circuit device, comprising:
- a main region on which a main circuit is formed;
- and
- a spare cell region for logic modification of the circuit formed on the main region,
- said spare cell region including a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer,
- each of said plurality of bypass wires having a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.
A semiconductor integrated circuit device, comprising:
- a plurality of P-channel transistor regions whose channel widths are different from each other;
- a plurality of N-channel transistor regions whose channel widths are different from each other;
- a plurality of gate electrodes for P-channel transistors located across the P-channel transistor regions;
- a plurality of gate electrodes for N-channel transistors located across the N-channel transistor regions;
- a plurality of bypass wires located between the P-channel transistor regions and the N-channel transistor regions;
- and
- a main wire layer formed at a different layer from that on which the bypass wires are formed,
- each of said plurality of bypass wires having a structure that can be connected to the main wire layer at more than one point.
A semiconductor integrated circuit device, comprising:
- a P-channel transistor region;
- an N-channel transistor region;
- a plurality of gate electrodes for P-channel transistors formed on the P-channel transistor region arranged in parallel with a predetermined constant pitch;
- a plurality of gate electrodes for N-channel transistors formed on the N-channel transistor region arranged in parallel with said predetermined constant pitch;
- a plurality of bypass wires located between the P-channel transistor region and the N-channel transistor region arranged in parallel with said predetermined constant pitch;
- and
- a main wire layer formed at a different layer from that on which the bypass wires are formed,
- each of said plurality of bypass wires having a structure that can be connected to the main wire layer at more than one point.
Dependencies are inferred from the claim text.