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US 7,504,851 B2Granted
Fault tolerant asynchronous circuits
AssigneeAchronix Semiconductor Corporation
InventorsRajit Manohar, Clinton W. Kelly
Life of this patent
Estimating the term…
Abstract
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
Claims19
A fault tolerant asynchronous circuit, comprising:
- a first logic circuit for receiving an input signal to generate an output signal;
- a second logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal;
- and
- a staticizer circuit, comprising first and second C-elements each connected to receive the output signal from each of the first and second logic circuits, and third and fourth C-elements each connected through inverters to an output of each of the first and second C-elements and to an output of each of the first and second logic circuits, each inverter connecting a pair of the C-elements to physically space the input and output of the pair of the C-elements.
1 more element
A method of fabricating a fault tolerant asynchronous circuit, comprising:
- providing a first logic circuit for receiving an input signal to generate an output signal;
- providing a second logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal;
- and
- providing a staticizer circuit, comprising first and second C-elements each connected to receive the output signal from each of the first and second logic circuits, and third and fourth C-elements each connected through inverters to an output of each of the first and second C-elements and to an output of each of the first and second logic circuits, each inverter connecting a pair of the C-elements to physically space the input and output of the pair of the C-elements.
1 more element
A fault tolerant asynchronous circuit, comprising:
- a first logic circuit for receiving an input signal to generate an output signal;
- a second logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal;
- a third logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal;
- and
- a fourth logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal;
- a first combining circuit for combining outputs of each of said first and second logic circuits to generate the output signal;
- a second combining circuit for combining outputs of each of said third and fourth logic circuits to generate the output signal;
- and
- a staticizer circuit, comprising first and second C-elements each connected to receive an output signal from each of the first and second combining circuits, and third and fourth C-elements each connected to an output of each of the first and second C-elements and an output of each of the first and second combining circuits.
6 more elements
A staticizer circuit for use with a logic or memory circuit to provide SEE immunity to the logic or memory circuit, comprising:
- a first circuit branch comprising a first C-element and a first pair of series-chain-connected inverters connected to an output of the first C-element;
- a second circuit branch comprising a second C-element and a second pair of series-chain-connected inverters connected to an output of the second C-element;
- and
- a third circuit branch comprising a third C-element and a third pair of series-chain-connected inverters connected to an output of the third C-element, two inputs of the first C-element being. connected to the second and third inverter pairs, two inputs of the second C-element being connected to the first and third inverter pairs, two inputs of the third C-element being connected to the first and second inverter pairs, and first and third circuit branches for receiving an input signal and a duplicate of the input signal, respectively, and for generating an output signal representative of the correct input signal, the output signal immune to transient single event effects (SEE) errors.
1 more element
Dependencies are inferred from the claim text.