Nano-liquid crystal on silicon (LCOS) chip having reduced noise

A liquid crystal on silicon (LCoS) chip comprising:

• a silicon substrate having an array of memory cells formed thereon;
• a first polycrystalline silicon layer disposed over said silicon substrate and forming a plurality of word lines extending in parallel across said memory cells;
• a first metal layer disposed above said first polycrystalline silicon layer and forming a plurality of bit lines extending in parallel across said memory cells, said bit lines being directed orthogonal to said word lines;
• and
• a second polycrystalline silicon layer disposed between said first polycrystalline silicon layer and said first metal layer and having shield portions located between the intersections of said bit lines and word lines, wherein said second polycrystalline layer includes a first plurality of first capacitor plates;
• a third polycrystalline silicon layer disposed between said first and second polycrystalline silicon layers and forming a second plurality of second capacitor plates disposed below said first capacitor plates and above regions of said silicon substrate not covered by said word lines, said first and second capacitor plates forming capacitor storage nodes of said memory cells,
• wherein cross-talk between the word lines and the bit lines is reduced.

A liquid crystal on silicon (LCoS) chip comprising:

• a silicon substrate having an array of memory cells formed thereon;
• and
• a first metal layer deposited over the silicon substrates and including a plurality of bit lines and a plurality of bit line shields, each of said bit line shields reducing cross-talk between adjacent two of the bit lines and being grounded;
• a first polycrystalline silicon layer disposed between said silicon substrate and said first metal layer forming a plurality of word lines extending in parallel across said memory cells, said word lines being directed orthogonal to said bit lines;
• a second polycrystalline silicon layer deposited between said first polycrystalline silicon layer and said first metal layer and having shield portions located between the intersections of said bit lines and word lines and a plurality of first capacitor plates;
• and
• a third polycrystalline silicon layer deposited between said first and second polycrystalline silicon layers and forming a plurality of second capacitor plates disposed below said first capacitor plates and above regions of said substrate not covered by said word lines, said first and second capacitor plates forming capacitor storage nodes of the memory cells.