Seal ring structures with unlanded via stacks
AssigneeSemiconductor Manufacturing International (Shanghai) Corporation
InventorXian J. Ning
Life of this patent
Estimating the term…
Abstract
Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.
Claims28
An integrated circuit device, the device comprising:
- a semiconductor substrate;
- an integrated circuit;
- a dielectric layer;
- a sealing structure surrounding the integrated circuit and disposed within the dielectric layer to prevent damage to the integrated circuit, the sealing structure comprising:
- a plurality of metal traces organized in vertical layers;
- and
- a plurality of vias, each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers, and each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces, and
- a barrier layer between the dielectric layer and each of the plurality of metal traces and plurality of vias,
- wherein the plurality of metal traces and plurality of vias form a continuous boundary in the dielectric layer.
An integrated circuit device, the device comprising:
- a semiconductor substrate;
- an integrated circuit;
- a dielectric layer;
- and
- a sealing structure surrounding the integrated circuit and disposed within the dielectric layer to prevent damage to the integrated circuit, the sealing structure comprising:
- a plurality of metal traces organized in vertical layers;
- and
- a plurality of vias, each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers, and each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces,
- wherein the plurality of vias each directly couple to at least 20% of a top surface of the two orthogonal surfaces and wherein the plurality of metal traces and plurality of vias form a continuous boundary in the dielectric layer.
An integrated circuit device, the device comprising:
- a semiconductor substrate;
- an integrated circuit;
- a dielectric layer;
- a sealing structure surrounding the integrated circuit and disposed within the dielectric layer, the sealing structure comprising:
- a first metal trace;
- a second metal trace, the second metal trace underlying a portion of the first metal trace;
- and
- a via coupling the first metal trace to the second metal trace, and
- a barrier layer between the dielectric layer and each of the first metal trace, second metal trace, and the via,
- wherein the via is coupled to a first surface of the second metal trace and a second surface of the second metal trace, and
- the first surface and the second surface are orthogonal.
An integrated circuit device, the device comprising:
- a semiconductor substrate
- an integrated circuit
- a dielectric layer;
- a sealing structure surrounding the integrated circuit and disposed within the dielectric layer, the sealing structure comprising:
- a first metal trace;
- a second metal trace, the second metal trace underlying a portion of the first metal trace;
- and
- a via coupling the first metal trace to the second metal trace, and
- wherein the via is coupled to a first surface of the second metal trace and a second surface of the second metal trace, the first surface and the second surface being orthogonal, the via directly coupled to at least 20% of the first surface, the first surface being a top surface of the second metal trace.
An integrated circuit device, the device comprising:
- a semiconductor substrate;
- an integrated circuit;
- and
- a sealing structure disposed around the integrated circuit, the sealing structure comprising:
- a first metal trace;
- a second metal trace, the second metal trace underlying the first metal trace;
- a via disposed between the first metal trace and second metal trace;
- and
- a portion of the via disposed beyond a distal surface of the second metal trace and below a top surface of the second metal trace, the distal surface and the top surface of the second metal trace being orthogonal,
- wherein the via couples a bottom surface of the first metal trace to both the top and distal surfaces and the distal of the second metal trace, the via directly coupled to at least 20% of the top surface and at least 10% of the distal surface.
An integrated circuit device, the device comprising:
- a semiconductor substrate;
- a dielectric layer;
- an integrated circuit;
- and
- a sealing structure disposed around the integrated circuit, the sealing structure comprising:
- a first metal trace;
- a second metal trace, the second metal trace underlying the first metal trace;
- a via disposed between the first metal trace and second metal trace;
- and
- a portion of the via disposed beyond a distal surface of the second metal trace and below a top surface of the second metal trace, the distal surface and the top surface of the second metal trace being orthogonal, and
- a barrier layer between the dielectric layer, the first metal trace, the second metal trace, and the via,
- wherein the via couples a bottom surface of the first metal trace to both the top and distal surfaces and the distal of the second metal trace.
Dependencies are inferred from the claim text.