Methods and apparatus for compiler managed first cache bypassing
AssigneeIntel Corporation
InventorsYoufeng Wu, Li-Ling Chen
Life of this patent
Estimating the term…
Abstract
Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.
Claims54
A method of compiling a software program to decrease misses of a first cache comprising:
- identifying a load instruction having an expected latency greater than or equal to a threshold;
- requesting that the load instruction be scheduled to have a first latency;
- scheduling the software program;
- comparing an actual latency associated with the load instruction in the scheduled software program to the first latency;
- and
- if the actual latency is greater than or equal to the first latency, marking the load instruction to bypass the first cache and access a lower level cache.
A method of compiling a software program to decrease misses of a first cache comprising:
- prior to scheduling the software, identifying a first set of load instructions for possibly bypassing the first cache;
- requesting scheduling of the software program such that the load instructions in the first set have at least a first latency;
- identifying a second set of load instructions in the scheduled software program having at least the first latency;
- and
- marking the second set of load instructions to bypass the first cache and access a lower level cache, wherein marking the second set of load instructions to bypass the first cache comprises marking the second set of load instructions to bypass the first cache if a bypass probability of the load instructions is greater than or equal to a probability threshold.
A compiler to reduce misses of a first cache by an executing software program comprising:
- a candidate load identifier to identify candidate load instructions for possibly bypassing the first cache;
- a scheduler to schedule the software program, wherein the scheduler requests to schedule each of the candidate load instructions to have a latency greater than or equal to a first threshold;
- a final load identifier to mark load instructions to bypass the first cache and access a lower level cache;
- an object code generator to develop object code from the scheduled software program, the object code incorporating the load instructions marked as bypassing the first cache by the final load identifier;
- and
- a memory cooperating with the object code generator to store the object code.
A tangible medium storing machine readable instructions comprising:
- first software, which, when executed by a machine, identifies candidate load instructions for possibly bypassing the first cache;
- second software, which, when executed by a machine, schedules the software program, wherein the second software request to schedule each of the candidate load instructions to have a latency greater than or equal to a first threshold;
- third software, which, when executed by a machine, marks load instructions to bypass the first cache and access a lower cache;
- and
- fourth software, which, when executed by a machine, develops object code from the scheduled software program, the object code incorporating the load instructions marked to bypass the first cache by the third software.
Dependencies are inferred from the claim text.