Sanity checker for integrated circuits

A method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising:

• automatically reading one or more netlists generated from one or more layouts;
• parsing the netlists of one or more different data formats into a predetermined data format;
• identifying one or more sub-circuits in the netlists isomorphic to at least one of the predefined sub-circuits;
• identifying one or more device parameters for sanity checking the identified sub-circuits;
• performing one or more predetermined calculations on the identified device parameters, wherein one of the predetermined calculations includes a leakage strength calculation to identify a worst case leakage path;
• and
• comparing one or more results from the predetermined calculations against the predefined checking criteria.

A method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising:

• reading one or more netlists generated from one or more layouts;
• identifying one or more sub-circuits in the netlists isomorphic to at least one of the predefined sub-circuits;
• identifying one or more device parameters for sanity checking the identified sub-circuits;
• performing one or more predetermined calculations on the identified device parameters, wherein one of the predetermined calculations includes a leakage strength calculation to identify a worst case leakage path;
• and
• comparing one or more results from the predetermined calculations against the predefined checking criteria.