Decoder using a memory for storing state metrics implementing a decoder trellis

A decoder comprising:

• a memory storing a plurality state metrics implementing a decoder trellis;
• and
• a processor configured to (i) calculate a plurality of first branch metrics for a first half of a plurality of path segments in said decoder trellis in response to a signal received by said decoder, (ii) calculate a plurality of second branch metrics for a second half of said path segments based upon said first branch metrics and (iii) update said state metrics in response to said first branch metrics and said second branch metrics, wherein each particular first branch metric of said first branch metrics has a complementary second branch metric of said second branch metrics such that a sum of said particular first branch metric and said complementary second branch metric equals a constant.