Semiconductor memory device

A semiconductor memory device having an error correction function of correcting a defective bit, comprising:

• a counter that counts the number of error corrections;
• an upper limit setting section that changes an upper limit of the number of error corrections in response to an upper limit setting signal inputted externally;
• a comparator that compares the number of error corrections with the upper limit;
• and
• an output section that generates an alarm if the number of error corrections reaches the upper limit during a test operation, wherein the upper limit setting section changes the upper limit according to generation of the alarm, and then detects an approximate number of error corrections based on whether or not the generation of the alarm has changed, and resets the upper limit.