Processor instruction retry recovery

A method for recovery of a processor core in a chip of a symmetric multiprocessing system, the chip having a processor core and a host firmware for supervising resource allocation and error recovery, comprising the steps of:

• providing a clock signal to recovery circuits;
• detecting a presence of an active long duration instruction, wherein the active long duration instruction comprises one of a store conditional or a cache-inhibited load instruction;
• allowing a checkpoint to advance one instruction group based on said detecting;
• determining whether an error may affect a result of the long duration instruction;
• blocking checkpointing in response to the determining that the error may affect a result of the long duration instruction
• quiescing a cache functional unit;
• establishing a coherent checkpoint in response to quiescing the cache functional unit;
• logically removing the processor core from the symmetric multiprocessing system in response to quiescing the cache functional unit and establishing a coherent checkpoint;
• resetting the processor core;
• restoring a nearest checkpoint to the processor core after resetting the processor core;
• indicating an interrupt;
• executing a preprogrammed number of instruction groups in a reduced execution mode;
• and
• executing at least one instruction group in a normal execution mode.