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US 7,467,316 B2Granted
System for clock synchronization for modules in an analytical device
AssigneeAgilent Technologies, Inc.
InventorRobert P. Rhodes
Life of this patent
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Abstract
A system for synchronizing clock signals in an analytical device includes a first module including a timing command generator configured to generate a command signal, the command signal related to a master clock signal, and a second module including a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal. The second module includes a clock generator configured to receive the timing reference signal and the local clock signal and is configured to adjust a timing output of the second module so that the timing of the second module is synchronized to the master clock signal.
Claims18
A system for synchronizing clock signals in an analytical device, comprising:
- a first module including a timing command generator configured to generate a command signal, the command signal related to a master clock signal;
- a second module including a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal, wherein the second module includes a clock generator configured to receive the timing reference signal and the local clock signal and is configured to adjust a timing output of the second module so that the timing of the second module is synchronized to the master clock signal;
- a counter configured to determine a number of pulses of the local clock signal that occur between a first pulse and second pulse of the timing reference signal;
- an adder configured to determine a difference between the number of pulses of the local clock signal that occur between the first pulse and second pulse of the timing reference signal and a minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;
- a register configured to add the excess local clock cycles to the ancillary (ADC) clock signal and provide a first result;
- and
- a comparator configured to compare the output of the register with a threshold value, wherein when the output of the register exceeds the threshold value, the comparator causes the ancillary (ADC) clock signal to be extended and causes the threshold value to be subtracted from the register, wherein any remainder in the register is applied to a subsequent ancillary (ADC) clock signal cycle.
4 more elements
A system for synchronizing clocks in an analytical device, comprising:
- a timing command generator configured to generate a command signal, the command signal related to a master clock signal;
- a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal;
- a counter configured to determine a number of pulses of the local clock signal that occur between a first and second pulse of the timing reference signal;
- an adder configured to determine a difference between the number of pulses of the local clock signal that occur between a first pulse and a second pulse of the timing reference signal and a minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;
- a register configured to add the excess local clock cycles to the ancillary (ADC) clock signal and provide a first result;
- and
- a comparator configured to compare the output of the register with a threshold value, wherein when the output of the register exceeds the threshold value, the comparator causes the ancillary (ADC) clock signal to be extended and causes the threshold value to be subtracted from the register, wherein any remainder in the register is applied to a subsequent ancillary (ADC) clock signal cycle.
4 more elements
A method for synchronizing clocks in an analytical device, comprising:
- generating a command signal, the command signal related to a master clock signal;
- generating a timing reference signal related to the command signal and a local clock signal;
- determining a number of pulses of the local clock signal that occur between a first pulse and a second pulse of the timing reference signal;
- determining a minimum number of local clock cycles to generate an ancillary (ADC) clock signal;
- determining a difference between the number of pulses of the local clock signal that occur between the first pulse and the second pulse of the timing reference signal and the minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;
- adding the excess local clock cycles to the ancillary (ADC) clock signal to provide a first result;
- and
- comparing the first result with a threshold value, wherein when the first result exceeds the threshold value, modifying the ancillary (ADC) clock signal and subtracting the threshold value from the first result;
- and
- applying any remainder after the subtraction to a subsequent ancillary (ADC) clock signal cycle.
7 more elements
Dependencies are inferred from the claim text.