Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited

A method of freezing at least a portion of processing within a processor supporting multiple independent resources from a common pipeline, the method comprising:

• determining assertion of at least one bit of a freeze register within the processor;
• inhibiting context switching of downstream resources within the processor;
• preventing further flow of information from a common FIFO to the downstream resources;
• inhibiting further requests from at least one state machine within a common pipeline portion of the processor;
• and
• acknowledging a freeze state.

An apparatus for freezing at least a portion of processing within a processor supporting multiple independent resources from a common pipeline, the apparatus comprising:

• a freeze register configured to receive a write of at least one predetermined freeze bit;
• a context controller configured to inhibit context switching of downstream resources coupled to the processor in response to the assertion of the at least one predetermined freeze bit;
• and
• a state monitor to determine assertion of the at least one predetermined freeze bit, initiate a freeze operation in at least one common processing portion, and configured to assert at least one acknowledge bit in an acknowledge register.