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US 7,467,254 B2Granted
Semiconductor memory device with write protected memory banks
AssigneeInfineon Technologies AG
InventorJean-Marc Dortu
Life of this patent
Estimating the term…
Abstract
The invention provides a semiconductor memory device that includes at least two memory banks. The semiconductor memory device is designed in such a way that: at least two processor units can carry out read accesses and write accesses to memory banks; and by means of an inhibit command communicated by one of the processor units, the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally. A circuit arrangement including the above semiconductor memory device is furthermore proposed.
Claims13
A semiconductor memory device, comprising:
- at least two memory banks;
- wherein the semiconductor memory device is configured such that at least two processor units can carry out read accesses and write accesses to the memory banks and, by means of an inhibit command communicated by one of the processor units, the write access to the inhibited memory bank by at least one of the processor unit which has communicated the inhibit command and the other processor unit to the inhibited memory bank is prevented at least occasionally;
- a control circuit adapted to set, based on an inhibit command, which of the at least two processor units is prioritized, in case of an access collision, when the two processors attempt to access the same memory bank;
- and
- a register circuit, which can be configured with the aid of the inhibit command in such a way that the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally,
- wherein the register circuit is further configured with an item of information regarding which of the processor units is prioritized for an access in the case of an access collision.
3 more elements
A circuit arrangement comprising:
- a semiconductor memory device including at least two memory banks;
- at least two processor units designed in such a way that they can carry out read accesses and/or write accesses to the memory banks;
- at least one of the processor units being configured in such a way that it can communicate an inhibit command to at least one of the memory banks, and by means of the communicated inhibit command, the write access by at least one of the processor units to the inhibited memory bank is prevented at least occasionally;
- a control circuit adapted to set, based on the inhibit command, which of the at least two processor units is prioritized, in case of an access collision, when the two processors attempt to access the same memory bank;
- and
- a register circuit, which can be configured with the aid of the inhibit command in such a way that the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally,
- wherein the register circuit is further configured with an item of information regarding which of the processor units is prioritized for an access in the case of an access collision.
4 more elements
A circuit arrangement comprising:
- a semiconductor memory device having at least two memory banks;
- at least two processor units that are adapted to carry out read accesses and write accesses to the at least two memory banks;
- a programmable control circuit in communication with the at least two memory banks and the at least two processor units, the control circuit being configured so that under prescribed circumstances the write access by one of the at least two processor units to one of the at least two memory banks is prevented at least occasionally;
- and
- a register circuit associated with the control circuit and configured to be programmed to select which of the at least two processor units is prioritized for an access in the case of an access collision where two processor units attempt to access the same memory bank;
- and
- the control circuit adapted to set, based on an inhibit command, which of the at least two processor units is prioritized, in case of an access collision, when the two processors attempt to access the same memory bank.
4 more elements
Dependencies are inferred from the claim text.