Flash memory data storage apparatus

A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising:

• a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width (FW) of the flash bus group and the bus width (HW) of the host bus group each represents a number of bus lines that transceive data in parallel in response to a same clock signal;
• a buffer memory that temporarily stores transferred data;
• a host interface that controls data transmission between the host bus group and the buffer memory;
• and
• a flash interface that controls data transmission between the flash bus group and the buffer memory, wherein the flash interface includes first through n'th flash input buffers that transfer data to the flash memory in stages in response to first through n'th transfer control clock signals, where n≧2, wherein, in a stage of the stages, an i'th flash input buffer of the first through n'th flash input buffers, where 2≦i≦n, receives data from an (i−1)'th flash input buffer, and provides data through i'th input-buffer bus groups to the flash memory in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of (i−1)'th input-buffer bus groups, wherein the first through n'th transfer control clock signals comprise an (i−1)'th transfer control clock signal and an i'th transfer control clock signal that is the (i−1)'th transfer control clock signal having a lengthened period, wherein a period (Ti) of the i'th transfer control clock signal applied to the i'th flash input buffer is longer than a period (Ti−1) of the (i−1)'th transfer control clock signal applied to the (i−1)'th flash input buffer, and wherein the Ni is obtained by dividing the bus width (FW) of the flash bus group by the bus width (IBWi) of the each of the i'th input-buffer bus groups.

A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising:

• a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width (FW) of the flash bus group and the bus width (HW) of the host bus group each represents a number of bus lines that transceive data in parallel in response to a same clock signal;
• and
• a flash interface that controls a data transmission operation between the flash bus group and the host bus group, wherein the flash interface includes first through n'th flash input buffers that transfer data to the flash memory in stages in response to first through n'th transfer control clock signals, where n≧2, and wherein an i'th flash input buffer, where 2≦i≦n, provides data through i'th input-buffer bus groups in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of (i−1)'th input-buffer bus groups, wherein a period (Ti) of an i'th transfer control clock signal is longer than a period (Ti−1) of an (i−1)'th transfer control clock signal, wherein the Ni is obtained by dividing the bus width (FW) of the flash bus group by the bus width (IBWi) of the each of the i'th input-buffer bus groups, wherein the bus width (IBWi) is twice the bus width (IBWi−1), wherein the period (Ti) is twice the period (Ti−1), wherein the flash interface further comprises a control clock generator that supplies the first through n'th transfer control clock signals, and wherein the control clock generator comprises:
• a reference clock generator that supplies a j 'th transfer control clock signal;
• and
• a period modulator that varies a period of the j 'th transfer control clock signal and that provides the first through n'th transfer control clock signals, wherein j is (n1)/2 when n is an odd number, and wherein j is n/2 when n is an even number.

A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising:

• a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width (FW) of the flash bus group and the bus width (HW) of the host bus group each represents a number of bus lines that transceive data in parallel in response to a same clock signal;
• and
• a flash interface that controls a data transmission operation between the flash bus group and the host bus group, wherein the flash interface includes first through n'th flash input buffers that transfer data to the flash memory in stages in response to first through n'th transfer control clock signals, where n≧2, and wherein an i'th flash input buffer, where 2≦i≦n, provides data through i'th input-buffer bus groups in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of an (i−1)'th input-buffer bus groups, wherein a period (Ti) of an i'th transfer control clock signal is longer than a period (Ti−1) of an (i−1)'th transfer control clock signal, wherein the Ni is obtained by dividing the bus width (FW) of the flash bus group by the bus width (IBWi) of the each of the i'th input-buffer bus groups, wherein the flash interface further comprises:
• an output buffer that transfers data from the flash memory to output-buffer bus groups, which is in number of the Ni, in response to the n'th transfer control clock signal;
• and
• a flash output multiplexer that selects one of the output-buffer bus groups in sequence and provides data from the selected output-buffer bus group for the external system, in response to clock pulses in the first transfer control clock signal every Ni pulses.

A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising:

• a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width (FW) of the flash bus group and the bus width (HW) of the host bus group each represents a number of bus lines that transceive data in parallel in response to a same clock signal;
• a buffer memory that temporarily stores transferred data;
• a host interface that controls data transmission between the host bus group and the buffer memory;
• and
• a flash interface that controls data transmission between the flash bus group and the buffer memory, wherein the flash interface includes first through n'th flash input buffers that transfer data to the flash memory in stages in response to first through n'th transfer control clock signals, where n≧2, and wherein an i'th flash input buffer, where 2≦i≦n, provides data through i'th input-buffer bus groups in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of (i−1)'th input-buffer bus groups, wherein a period (Ti) of an i'th transfer control clock signal is longer than a period (Ti−1) of an (i−1)'th transfer control clock signal, wherein the Ni is obtained by dividing the bus width (FW) of the flash bus group by the bus width (IBWi) of the each of the i'th input-buffer bus groups, wherein the buffer memory comprises:
• first and second temporary storage units that each transceive data, which is composed of a bus width of the host bus group, with the host interface and the flash interface;
• and
• a buffering multiplexer that provides data of the host bus group from the host interface for an alternative one of the first and second temporary storage units, and that provides data from the first and second temporary storage units for an alternative one of the host interface and the flash interface, wherein each of the first and second temporary storage units includes an SRAM storing data with the bus width (FW) of the flash bus group, wherein the host interface comprises a chip selection multiplexer that provides first and second storage enable signals for the buffering multiplexer by de-multiplexing a chip enable signal provided from the external system in response to a selection address, the first storage enable signal controlling data to be provided from the external system for the first temporary storage unit, the second storage enable signal controlling data to be provided from the external system for the second temporary storage unit, and wherein the host interface further comprises a host output multiplexer that selects one of data groups provided from the first and second temporary storage units, and provides the selected data group for the external system.