Timeouts on accessing a shared resource
AssigneeHewlett-Packard Development Company, L.P.
InventorRichard Brabant
Life of this patent
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Abstract
A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared register and able to communicate with both the first and second processors. A timeout error is generated responsive to the processor access timer exceeding a processor predetermined timeout threshold value.
Claims18
A computer-implemented method of generating timeout errors based on shared register access by at least two processors comprising a portion of a network switch, comprising:
- starting a processor access timer of the network switch responsive to generation of an access request by a first processor of the network switch;
- transmitting the generated first processor access request to a shared storage component comprising a portion of the network switch including a shared register and able to communicate with both the first processor and another processor of the network switch, wherein the shared storage component arbitrates read access to the shared register between the first processor and the other processor;
- and
- generating a timeout error responsive to the processor access timer exceeding a processor predetermined timeout threshold value based on the time required for an access request to be handled by the shared register.
A computer-implemented method of generating timeout errors based on shared register access by at least two processors, comprising:
- starting a processor access timer responsive to generation of an access request by a first processor;
- wherein the first processor access request is received by an interface component of a shared storage component;
- transmitting the generated first processor access request to the shared storage component including a shared register, wherein the shared storage component is configured to communicate with the at least two processors;
- and
- generating a timeout error responsive to the processor access timer exceeding a processor predetermined timeout threshold value, wherein the processor predetermined timeout threshold value is based on a second processor predetermined timeout threshold value and a register access predetermined timeout threshold value.
Dependencies are inferred from the claim text.