US 7,467,243 B2 · Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip

Abstract

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Claims38

Dependent claims

An advanced processor having a plurality of processor cores connected to a plurality of fast messaging ring components, the fast messaging ring components comprising:

a ring input coupled to an insertion queue and a receive queue, and a multiplexer;
the multiplexer having a first input coupled to the ring input by way of the insertion queue and configured to provide a ring output;
a transmit queue coupled to a second input of the multiplexer;
a plurality of receive buffers coupled to the receive queue;
a plurality of transmit buffers coupled to the transmit queue;
and a plurality of registers;
said fast messaging ring components being connected together in a ring configuration;
in which each processor core is connected to its own individual fast messaging ring component, and in which each processor core is not always required to participate in exchanging messages on said fast messaging ring component when said fast messaging ring is transmitting messages between a prior ring component and a next ring component.

5 more elements

Dependencies are inferred from the claim text.

Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip

Life of this patent

Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip

Life of this patent

Abstract

Claims38