Method and system for dynamic FIFO flow control
AssigneeVIA Technologies, Inc.
InventorHsilin Huang
Life of this patent
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Abstract
Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.
Claims50
A method of optimally performing read operations in a first FIFO device with a control circuit coupled to the first FIFO device, the method comprising:
- a) detecting an asserted read enable signal at the first FIFO device, wherein a first read pointer holds an address to the data entry to be read in a first FIFO memory in the first FIFO device;
- b) detecting one or more obsolete data entries starting at the address held by the first read pointer;
- c) loading the address of the next valid data entry into the first read pointer;
- d) receiving a valid entry at the control circuit;
- and
- e) determining whether the received valid entry is a header entry.
A method of optimally performing read operations in a first FIFO device with a control circuit coupled to the first FIFO device, the method comprising:
- detecting an asserted read enable signal at the first FIFO device, wherein a first read pointer holds an address to the data entry to be read in a first FIFO memory in the first FIFO device;
- checking a first identification tag of the data entry;
- detecting one or more obsolete data entries starting at the address held by the first read pointer;
- loading the address of the next valid data entry into the first read pointer;
- and
- detecting an asserted write enable signal at the first FIFO device, wherein a first write pointer holds an address to be written to in the first FIFO memory.
A method of optimally performing write operations in a first FIFO device with a control circuit coupled to the first FIFO device, the method comprising:
- a) detecting an asserted write enable signal at the first FIFO device, wherein a first write pointer holds an address to be written to in the first FIFO memory;
- b) detecting one or more obsolete data entries starting at the address held by the first write pointer;
- c) loading the address of the next valid data entry into the first write pointer;
- d) receiving a valid entry at the control circuit;
- and
- e) determining whether the received valid entry is a header entry.
Dependencies are inferred from the claim text.