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US 7,467,177 B2Granted
Mathematical circuit with dynamic rounding
AssigneeXilinx, Inc.
InventorsJames M. Simkins, Steven P. Young, Jennifer Wong, Bernard J. New, Alvin Y. Ching
Life of this patent
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Abstract
Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
Claims30
A DSP slice in an array of DSP slices comprising:
- a first operand input port for receiving a first signed operand, the first signed operand including a first sign bit;
- a second operand input port for receiving a second signed operand, the second signed operand including a second sign bit;
- wherein the first signed operand is a value selected from a group consisting of an upstream-output-cascade value from another DSP slice upstream from the DSP slice, a concatenated value of another first signed operand and another second signed operand from the other DSP slice upstream from the DSP slice, a partial product value from the other DSP slice upstream from the DSP slice, a product value from the other DSP slice upstream from the DSP slice, and an output value from the other DSP slice upstream from the DSP slice;
- a third operand input port for receiving a rounding constant;
- a product generator having:
- a multiplier port connected to the first operand input port for receiving the first signed operand;
- a multiplicand port connected to the second operand input port for receiving the second signed operand;
- and
- a product port for producing a product of the first and second signed operands;
- a correction circuit having:
- first and second correction-circuit input terminals connected to the respective first and second operand input ports for receiving the first and second sign bits;
- and
- a correction-circuit output terminal, the correction circuit configured for generating a correction factor from the first and second sign bits for providing the correction factor on the correction-circuit output terminal;
- and
- a adder having a first addend terminal connected to the product port for receiving the product, a second addend terminal connected to the third operand input port for receiving the rounding constant, and a third addend terminal connected to the correction-circuit output terminal for receiving the correction factor;
- the adder configured to sum the rounding constant, the correction factor, and the product to obtain a rounded product.
13 more elements
A circuit comprising:
- a first operand port providing a multiplier;
- a second operand port providing a multiplicand;
- a third operand port providing a rounding constant;
- a product generator having a multiplier port connected to the first operand port for receiving the multiplier, a multiplicand port connected to the second operand port for receiving the multiplicand, and a product port, wherein the product generator provides a signed product of the multiplier and the multiplicand on the product port;
- and
- an adder having a first addend port connected to the product port and receiving the product, a second addend port connected to the third operand port for receiving the rounding constant, a carry-in port, and a sum port;
- wherein the circuit is a DSP slice;
- wherein the multiplier associated with a first signed operand, the first signed operand being a value selected from a group consisting of an upstream-output-cascade value from another DSP slice upstream from the DSP slice, a concatenated value from the other DSP slice, a partial product value from the other DSP slice, a product value from the other DSP slice, and an output value from the other DSP slice;
- and
- wherein the adder is configured to sum the rounding constant, the correction factor, and the product to obtain a rounded product.
7 more elements
A circuit comprising:
- a first operand port providing a multiplier;
- a second operand port providing a multiplicand;
- a third operand port providing a rounding operand;
- a product generator having a multiplier port connected to the first operand port for receiving the multiplier, a multiplicand port connected to the second operand port for receiving the multiplicand, and a product port, wherein the product generator provides a product of the multiplier and the multiplicand on the product port;
- carry-in logic receiving a carry-in signal, a first sign bit from the multiplier, and a second sign bit from the multiplicand;
- and
- an adder having a first addend port connected to the product port for receiving the product, a second addend port connected to the third operand port for receiving the rounding operand, a carry-in port connected to the carry-in logic, and a sum port;
- wherein the circuit is a DSP slice;
- wherein the multiplier is a value selected from a group consisting of an upstream-output-cascade value from another DSP slice upstream from the DSP slice, a concatenated value of another multiplier and another multiplicand from the other DSP slice upstream from the DSP slice, a partial product value from the other DSP slice upstream from the DSP slice, a product value from the other DSP slice upstream from the DSP slice, and an output value from the other DSP slice upstream from the DSP slice;
- wherein the adder is configured to sum at least the rounding operand and the product to obtain a rounded product.
7 more elements
An array of DSP elements comprising:
- a DSP element in the array of DSP elements having:
- a first operand input port for receiving a first signed operand, the first signed operand including a first sign bit;
- a second operand input port for receiving a second signed operand, the second signed operand including a second sign bit;
- wherein the first signed operand is a value selected from a group consisting of an upstream-output-cascade value from another DSP element upstream from the DSP element, a concatenated value of another first signed operand and another second signed operand from the other DSP element upstream from the DSP element, a partial product value from the other DSP element upstream from the DSP element, a product value from the other DSP element upstream from the DSP element, and an output value from the other DSP element upstream from the DSP element;
- a third operand input port for receiving a third signed operand from an output of an adjacent DSP element with respect to the DSP element, the third signed operand including a third sign bit;
- a fourth operand input port for receiving a fourth signed operand from an output of the DSP element, the fourth signed operand including a fourth sign bit;
- a fifth operand input port for receiving a rounding constant;
- a correction circuit having:
- first, second, third and fourth correction-circuit input terminals for receiving the first, second, third and fourth sign bits;
- and
- a correction-circuit output terminal, the correction circuit for generating a correction factor based on a selection from a group consisting of the first sign bit, a combination of the first and second sign bits, the third sign bit, and the fourth sign bit, and the correction circuit providing the correction factor on the correction-circuit output terminal;
- and
- a adder having a first addend terminal, a second addend terminal connected to the fifth operand input port for receiving the rounding constant, and a third addend terminal connected to the correction-circuit output terminal for receiving the correction factor;
- the adder configured to sum the rounding constant, the correction factor, and an input value on the first addend terminal to obtain a rounded value.
11 more elements
An arithmetic circuit comprising:
- a first operand input port for receiving a first signed operand, the first signed operand including a first sign bit;
- wherein the first signed operand is a value selected from a group consisting of an upstream-output-cascade value from another arithmetic circuit upstream from the arithmetic circuit, a concatenated value of another first signed operand and a second signed operand of the another arithmetic circuit upstream from the arithmetic circuit, a partial product value from the another arithmetic circuit upstream from the arithmetic circuit, a product value from the another arithmetic circuit upstream from the arithmetic circuit, and an output value from the another arithmetic circuit upstream from the arithmetic circuit;
- and wherein the value selected from the group is determined responsive to a mode setting of a mode circuit;
- a correction circuit having:
- an input terminal for receiving the first sign bit;
- and
- a correction-circuit output terminal, the correction circuit for generating a correction factor based on the first sign bit, and the correction circuit providing the correction factor on the correction-circuit output terminal;
- and
- an adder having a first addend terminal for receiving the first signed operand, a second addend terminal for receiving a rounding constant, and a third addend terminal connected to the correction-circuit output terminal for receiving the correction factor;
- the adder configured to sum the rounding constant, the correction factor, and the first signed operand to obtain a rounded value.
7 more elements
Dependencies are inferred from the claim text.