Saturation and rounding in multiply-accumulate blocks

A programmable logic resource comprising:

• at least one multiplier implemented using digital signal processing circuitry, the at least one multiplier comprising:
• multiplication circuitry that multiplies inputs to the multiplier,
• shifting circuitry coupled to the multiplication circuitry that shifts bits of an output of the multiplication circuitry,
• adder circuitry coupled to the shifting circuitry that adds an output of the shifting circuitry with a predefined value, and
• zeroing circuitry coupled to the adder circuitry that zeros a predetermined number of least significant bits of an output of the adder circuitry.