Programmable logic device with pipelined DSP slices

An integrated circuit comprising:

• a programmable interconnect;
• a plurality of DSP slices, each DSP slice including:
• a first operand input port programmably connected to the programmable interconnect and including a plurality of first operand input lines;
• a second operand input port programmably connected to the programmable interconnect and including a plurality of second operand input lines;
• a product generator having a first multiplier port for receiving a multiplier, a second multiplier port for receiving a multiplicand, and a product port;
• a first operand input circuit connected between the first operand input port and the first multiplier port, the first operand input circuit including first and second storage elements for each first operand input line of the plurality of first operand input lines;
• a second operand input circuit connected between the second operand input port and the second multiplier port, the second operand input circuit including third and fourth storage elements for each second operand input line;
• and
• an adder having a first addend port connected to the product port, a second addend port, and a sum port;
• and
• a configuration memory storing configuration data defining a circuit configuration, wherein:
• the first and second operand input circuits of a first of the DSP slices programmably connects the programmable interconnect to the first and second multiplier ports via one of the first and second storage elements for each said first and second operand input line;
• and
• at least one of the first and second operand input circuits of a second of the DSP slices programmably connects the programmable interconnect to the respective one of the first and second multiplier ports via both of the first and second storage elements for each said first and second operand input line.

An integrated circuit comprising:

• a plurality of configurable logic blocks;
• a programmable interconnect for programmably interconnecting the configurable logic blocks;
• a plurality of DSP slices, each DSP slice including:
• a first operand input port for being programmably connected to the programmable interconnect;
• a second operand input port;
• a product generator having a multiplier port, a multiplicand port, a first partial-product port, and a second partial-product port;
• a first operand input circuit connected between the first operand input port and the multiplier port, the first operand input circuit including first and second collections of one or more storage elements connected in series;
• a second operand input circuit connected between the second operand input port and the multiplicand port, the second operand input circuit including first and second collections of one or more storage elements connected in series;
• multiplexing circuitry having a first input port connected to the first partial-product port, a second input port connected to the second partial-product port, a bypass port, a feedback port, and first and second output ports;
• and
• an adder having a first addend port connected to the first output port of the multiplexing circuitry, a second addend port connected to the second output port of the multiplexing circuitry, and sum port;
• a product register having an input port, connected to the sum port, and a product port;
• and
• a feedback bus connected between the product port and the feedback port of the multiplexing circuitry;
• and
• a cascade bus connecting the product port of a first of the DSP slices via a multiplexer to the bypass port of a second of the DSP slices.

An integrated circuit comprising:

• a plurality of configurable logic blocks;
• a programmable interconnect for programmably interconnecting the configurable logic blocks;
• and
• a plurality of DSP slices, each DSP slice of the plurality of DSP slices including:
• a first operand input port for being programmably connected to the programmable interconnect;
• a second operand input port;
• a product generator having a multiplier port, a multiplicand port, and a product port;
• a cascade port of a first DSP slice of the plurality of DSP slices connected to a second DSP slice of the plurality of DSP slices which is upstream from the first DSP slice;
• multiplexing circuitry having:
• a first input port connected to the product port;
• a bypass port;
• a multiplexing-circuitry output port;
• and
• a select port for receiving mode control signals;
• and
• a shifter connected between the cascade port and the bypass port.

A method for updating operands in a DSP system, the DSP system including a programmable interconnect, at least one upstream DSP slice, at least one downstream DSP slice, each DSP slice including a first operand input port and first and second operand input registers connected between a second operand input port and the programmable interconnect, the method comprising:

• providing a first series of multiplier operands on the first operand input port;
• storing a first multiplicand operand in the second operand input register, the second operand input register applying the stored second operand to the second operand input port;
• multiplying each of the first series of multiplier operands by the first multiplicand operand stored in the second operand input register;
• storing a second multiplicand operand in the first operand input register while multiplying the first series of multiplier operands by the first multiplicand;
• providing a second series of multiplier operands on the first operand input port;
• providing the stored second multiplicand operand to the second operand input port;
• and
• multiplying each of the second series of multiplier operands by the second multiplicand operand.