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US 7,467,124 B2Granted
Arrangement of configurable logic blocks
AssigneeInfineon Technologies AG
InventorChristoph Heer
Life of this patent
Estimating the term…
Abstract
A logic circuit includes at least one register and a corresponding comparator coupled to the register and an input data node. A multiplexer is coupled to the register. A control block is coupled to the multiplexer, the comparator, the input node and an input control node.
Claims14
A logic circuit comprising:
- an input data node for carrying input data;
- a configurable logic block (CLB) control logic circuit having a first input, a second input, a third input, a fourth input and an output;
- at least one look-up table in which a switching function of at least one conditional branch is implemented with content addressability, wherein the at least one look-up table generates an “if then else” branch that realizes a comparison of the input data with comparison data previously stored in the at least one look-up table, and wherein a result output of the at least one look-up table is provided to a third input of the CLB control logic circuit;
- an input data bus coupled between the input data node and a bus input of the at least one look-up table, wherein the first input of the CLB control logic circuit is coupled to the input data node via the input data bus;
- at least one multiplexer having a control input coupled to the input data node and also to the first input of the CLB control logic circuit via at least part of the bit width of the input data bus, an output of the at least one multiplexer being coupled to a fourth input of the CLB control logic circuit;
- a control input node coupled via a control bus to the second input of the CLB control logic circuit;
- and
- at least one register data bus coupled between a register data bus output of the at least one look-up table and a bus input of the at least one multiplexer.
5 more elements
A logic circuit comprising:
- a register;
- a comparator with a first input coupled to the register and with a second input coupled to an input node;
- a multiplexer with an input coupled to the register;
- and
- a control block with inputs coupled to the multiplexer, the comparator, the input node and an input control node, wherein the logic circuit realizes an “if then else” branch based upon information carried at the input node and information stored in the register.
2 more elements
A logic circuit comprising:
- means for performing a switching function of at least one conditional branch is implemented with content addressability, wherein the means for performing a switching function generates an “if then else” branch that realizes a comparison of input data with previously stored comparison data;
- means, coupled to the means for performing a switch function, for selecting at least a portion of the comparison data;
- and
- a CLB control logic circuit having a first input coupled to receive at least a portion of the input data, a second input coupled to the means for performing a switching function, and a third input coupled to the means for selecting.
1 more element
Dependencies are inferred from the claim text.