Method and apparatus for aligning multiple outputs of an FPGA

A Field Programmable Gate Array (FPGA), comprising:

• gate logic configured to implement a plurality of data lanes, an individually adjustable preskew delay for each said data lane, a feedback channel via which an alignment indication of all data lanes may be received, and a skew value adjuster via which the preskew delay for each data lane may be individually adjusted;
• gate logic configured to enable the FPGA to isolate one of the data lanes for alignment by causing training data for the isolated data lane to be transmitted on the isolated data lane and causing a short fixed pattern to be transmitted on at least all unaligned data lanes,
• the short repetitive pattern being shorter than a capture range of a receiving device enabling the receiver to find a start of the deskew data on the other unaligned data lanes within the capture range for those data lanes, to cause the receiver to artificially determine that the other unaligned data lanes are aligned;
• gate logic configured to transmit deskew data, the deskew data including a portion of the training data to be used to align the isolated data lane as well as portions of the short repetitive pattern for each of the other unaligned data lanes;
• gate logic configured to adjust the preskew value of the isolated data lane until a feedback signal from the receiving device indicates that the communication lanes are aligned, the feedback signal being a collective feedback signal indicative as to whether the plurality of communication lanes have been aligned.