Layout and architecture for reduced noise coupling between circuitry and on-chip antenna

An integrated circuit for wireless communications, comprising:

• a monolithic semiconductor substrate having a plurality of integrated devices including at least one of a transmitter and a receiver disposed in or on said substrate;
• at least one on-chip balanced antenna formed in or on said substrate;
• and
• a balanced antenna feed structure electrically connecting said antenna to said transmitter or said receiver;
• wherein one of said plurality of integrated devices is a largest noise coupling contributor having a center of noise, and wherein said one said plurality of integrated devices is disposed on said substrate relative to said on-chip antenna such that the center of noise has distances relative to midpoint of respective members of said on-chip antenna, said distances being within ten (10) percent or less of one another.