Multi-stage phase detector
AssigneeXilinx, Inc.
InventorJames P. Ross
Life of this patent
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AssigneeXilinx, Inc.
InventorJames P. Ross
Estimating the term…
A multi-stage phase detector (four stages in one described embodiment) comprises a plurality of data paths and phase paths that are buffered from a received serial data input stream to reduce loading. Each data path recovers a data bit and further functions as a transition detector to detect consecutive data bits having similar logic states. An exclusive NOR gate in the data path produces a control signal to disable a multiplexer in the phase path when two data bits have similar logic states. Each phase path produces a sample of a serial data input stream and produces the sample to a multiplexer for coupling to a transconductance module. The multiplexer output is coupled to or decoupled from the transconductance module by the control signal from the data path to maintain phase-lock.
A phase-locked loop (PLL) for high data rate serial digital communications receiving serial data at a rate that exceeds one gigabits per second, the phase-locked loop comprising:
A programmable fabric phase-locked loop (PLL) for high data rate serial digital communications receiving serial data, the phase-locked loop comprising:
Dependencies are inferred from the claim text.