WLAN receiver having an iterative decoder

A wireless local area network (WLAN) receiver having high data throughput, the WLAN receiver comprises:

• a plurality of radio frequency (RF) receiving modules, wherein each of the plurality of the RF receiving modules is operably coupled to receive inbound RF signals and to convert the inbound RF signals into inbound digital symbols;
• and
• a baseband processing module operably coupled to:
• space and time decode the inbound digital symbols generated by the plurality RF receiver modules to produce M streams of symbols;
• convert the M streams of symbols from time domain symbols to frequency domain symbols to produce M streams of frequency domain symbols;
• demap the frequency domain symbols of the M streams of frequency domain symbols to produce streams of demapped data;
• multiplex the streams of demapped data into a serial stream of demapped data;
• decode the serial stream of demapped data to produce decoded data wherein the decoding includes:
• determining inner coded bits and extrinsic information of the inner coded bits based on the serial stream of demapped symbols, a channel matrix, and inner extrinsic information feedback;
• determining outer coded bits and extrinsic information of the outer coded bits based on the extrinsic information of the inner coded bits, the inner coded bits, and a soft input soft output decoding process;
• generating the inner extrinsic information feedback based on the extrinsic information of the outer coded bits;
• and
• producing decoded bits based on the outer coded bits;
• and
• descramble the decoded data to produce inbound data.

An iterative decoder for use in a wireless local area network (WLAN) receiver having high data throughput, the iterative decoder comprises:

• an inner decoder/detector operably coupled to produce a first output of inner coded bits and a second output of extrinsic information of the inner coded bits from symbol vector based on a channel matrix and inner extrinsic information feedback;
• a first subtraction module operably coupled to subtract the inner extrinsic information feedback from the extrinsic information of the inner coded bits to produce current inner extrinsic information;
• a deinterleaving module operably coupled to deinterleave the current inner extrinsic information to produce deinterleaved inner extrinsic information;
• a second deinterleaving module operably coupled to deinterleave the inner code bits to produce deinterleaved inner code bits;
• an outer decoder operably coupled to determine outer coded bits and extrinsic information of the outer coded bits from the deinterleaved inner code bits and the deinterleaved inner extrinsic information in accordance with a soft input soft output decoding process;
• a second subtraction module operably coupled to subtract the deinterleaved inner extrinsic information from the extrinsic information of the outer coded bits to produce current outer extrinsic information;
• an interleaving module operably coupled to interleave the current outer extrinsic information to produce the inner extrinsic information feedback;
• and
• a determining module operably coupled to produce decoded bits based on the outer coded bits.

A wireless local area network (WLAN) receiver having high data throughput, the WLAN receiver comprises:

• a plurality of radio frequency (RF) receiving modules, wherein each of the plurality of the RF receiving modules is operably coupled to receive inbound RF signals and to convert the inbound RF signals into inbound digital symbols;
• a space and time decoding module operably coupled to decode the inbound digital symbols generated by the plurality RF receiver modules to produce M streams of symbols;
• Fast Fourier Transform (FFT) module operably coupled to convert the M streams of symbols from time domain symbols to frequency domain symbols to produce M streams of frequency domain symbols;
• demapping module operably coupled to demap the frequency domain symbols of the M streams of frequency domain symbols to produce streams of demapped data;
• multiplexer operably coupled to multiplex the streams of demapped data into a serial stream of demapped data;
• iterative decoder operably coupled to decode the serial stream of demapped data to produce decoded data, wherein the iterative decoder includes:
• an inner decoder/detector operably coupled to determine inner coded bits and extrinsic information of the inner coded bits from the serial stream of demapped data based on a channel matrix and inner extrinsic information feedback;
• a first subtraction module operably coupled to subtract the inner extrinsic information feedback from the extrinsic information of the inner coded bits to produce current inner extrinsic information;
• a deinterleaving module operably coupled to deinterleave the current inner extrinsic information to produce deinterleaved inner extrinsic information;
• a second deinterleaving module operably coupled to deinterleave the inner code bits to produce deinterleaved inner code bits;
• an outer decoder operably coupled to determine outer coded bits and extrinsic information of the outer coded bits from the deinterleaved inner code bits and the deinterleaved inner extrinsic information in accordance with a soft input soft output decoding process;
• a second subtraction module operably coupled to subtract the deinterleaved inner extrinsic information from the extrinsic information of the outer coded bits to produce current outer extrinsic information;
• an interleaving module operably coupled to interleave the current outer extrinsic information to produce the inner extrinsic information feedback;
• and
• a determining module operably coupled to produce the decoded data based on the outer coded bits;
• and
• descrambling module operably coupled to descramble the decoded data to produce inbound data.