Apparatus and method of analyzing packetized data spanning over multiple clock cycles

Apparatus for processing packetized data spanning multiple clock cycles, comprising:

• a counter for counting cycles of a clock signal, said counter being responsive to said clock signal, to a Data Valid signal indicative of the presence of valid data, and to an SOP signal indicative of a start of a packet, said counter incrementing its clock cycle count in response to each of said clock cycles when said Data Valid signal is present, said counter having a range of counts equal to a length of said packet;
• a first comparator, for comparing a present clock cycle count to one of a plurality of reference clock cycle count values and producing a first enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said first comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter;
• a second comparator, for comparing said clock cycle count to one of a plurality of reference clock cycle count values and producing a second enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said second comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter;
• a word recognizer, for comparing a presently received digital word to a reference digital word and producing a determination of equality or non-equality in response to said first enable signal, thereafter said word recognizer being programmed with a second reference digital word for comparing a further received digital word to said second reference digital word and producing a determination of equality or non-equality in response to said second enable signal;
• and
• an output circuit for providing an indication of whether said digital word comparisons produced a determination of equality at each clock cycle corresponding to a reference clock cycle count value.

Method for processing packetized data spanning multiple clock cycles, comprising:

• counting cycles of a clock in a counter, said counter counting from a start of packet (SOP) signal only in response to a Data Valid signal indicative of the presence of valid data, said counter having a range equal to a length of a packet;
• comparing, at each of a plurality of comparators, a present clock cycle count from the counter to a reference clock cycle value and producing a respective enable signal at each of said comparators in response to a determination that said present cycle count equals its respective reference clock cycle value;
• enabling at least one word recognizer of a respective plurality of word recognizers in response to said respective enable signal;
• comparing, at at least one word recognizer, a presently received digital word from the packetized data to a reference digital word;
• providing, at an output of an enabled word recognizer, an indication of a favorable word comparison;
• and
• providing, at an output, a TRUE indication when said digital word comparisons produced a determination of equality at each clock cycle count from the counter corresponding to the reference clock cycle count value.