Row address controller

A row address controller comprising:

• a bank control unit for generating an active pulse and a precharge pulse in response to an active precharge signal, and for generating a word line clear signal and a block selection enable signal by using the active pulse and precharge pulse;
• an address decoder for latching and decoding a row address signal in response to a decoder enable signal, and for outputting the decoded signal as a first address signal and a second address signal;
• a block selection unit for generating a block selection signal in response to a redundancy signal, a repair signal, the word line clear signal, the block selection signal and the first address signal;
• a block control unit for generating a word line latch signal in response to the precharge pulse and the block selection signal;
• and
• a latch unit for latching and outputting the second address signal in response to the word line latch signal.