US 7,466,619 B2 · Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of banks #0 to #3, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.

Claims13

Dependent claims

A semiconductor memory device comprising:

a plurality of banks independently operable;
a predecoder that predecodes an address signal to generate a predecode signal including first and second portions;
first latch circuits, each of which is assigned to the plurality of banks, that hold the first portion of the predecode signal;
a main decoder that is assigned in common to at least two of the plurality of banks, and receives the second portion of the predecode signal and outputs of the first latch circuits, wherein
the main decoder includes second latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/760,959Filed 11 Jun 2007

Priority

JP 2006-1876967 Jul 2006

Published

US 2008/0008024 A110 Jan 2008

Granted

16 Dec 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 8/12
Arrangements for selecting an address in a digital store: group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 11/4087
Address circuits: address decoders, e.g. bit - or word line decoders; Multiple line decoders
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims13