Sense amplifier for non-volatile memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChin-Huang Wang
Life of this patent
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Abstract
A sense amplifier comprising a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit, a charge control circuit for providing a precharge signal based on the output of the sense output circuit and a sense enable signal, a latch control circuit for providing control of a latch circuit based on the sense signal, the precharge signal and the logical inverse of the sense output signal, wherein when the sense signal is read, the latch control circuit provides one or more predetermined signals to the latch circuit to latch the sense signal to a logical level.
Claims16
A sense amplifier comprising:
- a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit;
- a charge control circuit for providing a precharge signal based on the output of the sense output circuit and a sense enable signal;
- and
- a latch control circuit including a plurality of inverters and a NOR gate for selectively controlling a pull-up device and a pull-down device to maintain the sense signal at a predetermined voltage level in response to the sense signal, the precharge signal and the logical inverse of the sense output signal.
A sense amplifier comprising:
- a first inverter having an input connected to a sense node of a memory circuit;
- a second inverter whose input is connected to the output of the first inverter;
- a third inverter whose input is connected to the output of the second inverter and whose output is connected to a charge control circuit;
- a fourth inverter whose input is connected to the sense node;
- a fifth inverter whose input is connected to the output of the fourth inverter;
- a sixth inverter whose input is connected to the output of the fifth inverter and whose output is connected to the gate of a PMOS device having its source connected to a positive supply voltage and its drain connected to the sense node;
- and
- a NOR gate having one input connected to the output of the second inverter, a second input connected to the output of a charge control circuit and an output connected to the gate of an NMOS device whose drain is connected to the sense line and whose source is connected to a negative supply (GND).
A method for sensing the value of a memory cell comprising:
- receiving the sense signal from the memory cell;
- combining the sense signal with a precharge signal to generate a pull-up signal and a pull-down signal;
- applying the pull-up signal to a pull-up transistor connected between the sense signal and a positive supply voltage;
- and
- applying the pull-down signal to a pull-down transistor connected between the sense signal and a negative supply voltage,
- wherein when the sense signal changes during a memory read, feedback will be applied to the sense signal latching it to a logic level.
Dependencies are inferred from the claim text.