Sense amplifier for flash memory device

A method for a latch circuit within a sense amplifier, the method comprising:

• coupling a first latch supply node and a second latch supply node in the latch circuit to an equalization potential during an equalization mode;
• coupling the first latch supply node to a first power supply potential and the second latch supply node to a second power supply potential during a sense mode;
• coupling the first latch supply node to the first power supply potential and the second latch supply node to the second power supply potential during a read-out mode;
• and
• latching a data output of the sense amplifier and then floating the first latch supply node and the second latch supply node such that the latch uses substantially no power.

A sense amplifier circuit comprising:

• a latch circuit having a first signal node, a second signal node, a first latch power supply node and a second latch power supply node;
• an equalization circuit to couple an equalization potential to the first signal node, the second signal node, the first latch power supply node, and the second latch power supply node when the sense amplifier circuit is operating in an equalization mode;
• a sense circuit to couple the first latch power supply node to a first power supply potential and the second latch power supply node to a second power supply potential during a sense mode, the sense circuit to couple the first signal node to a first bitline signal and the second signal node to one of a second bitline signal, a complement of the first bitline signal, and a reference signal during a sense mode;
• a power supply circuit to couple the first power supply potential to the first latch power supply node and the second power supply potential to the second latch power supply node when the sense amplifier is operating in a read-out mode;
• a read-out circuit to output an output signal coupled to one of the first signal node and the second signal node during the read-out mode;
• and
• a high voltage switch to substantially preclude conduction between the first bitline signal and the first signal node, and the second bitline signal and the second signal node during a programming operation, the programming operation to produce on at least one of the first bitline signal and the second bitline signal a potential substantially exceeding a voltage range defined by the first power supply potential and the second power supply potential.

A sense amplifier circuit, comprising:

• a latch formed by a pair of cross-coupled inverters and having a first signal node, a second signal node, a first latch power supply node and a second latch power supply node;
• control circuitry, including an equalization circuit, responsive to an equalization control signal, configured to couple the first and second signal nodes together to an equalization potential that is close to a threshold of the latch and to isolate the first and second latch power supply nodes from respective first and second power supply potentials and couple the same to the equalization potential whenever the sense amplifier circuit is operating in an equalization mode;
• a pair of bitline transistors configured to couple a selected one of first and second memory bitlines to a respective one of the first and second signal nodes of the latch;
• a pair of reference current circuits coupled to respective signal nodes of the latch and responsive to control signals, to provide a reference current to a selected one of the first and second signal nodes in a delay mode of the sense amplifier circuit so as to develop a potential on the selected first or second signal node corresponding to a state of a selected memory cell on the selected memory bitline, the first and second latch power supply nodes remaining isolated from the respective first and second power supply potentials during the delay mode, the control circuitry, responsive to a sense control signal, to couple the first and second latch power supply nodes to the respective first and second power supply potentials in a sense mode at the conclusion of the delay mode such that the developed potential causes the latch to assume a state corresponding to the selected memory cell;
• and
• a readout circuit coupled to the first and second signal nodes of the latch so as to produce an output signal during a read-out mode from that one of the first and second signal nodes corresponding to the selected memory bitline.

A method of operating a sense amplifier latch circuit, comprising:

• in an equalization mode, isolating first and second latch power supply nodes of a latch from respective first and second power supply potentials, and coupling the first and second latch power supply nodes as well as first and second signal nodes of the latch to an equalization potential that is close to a threshold of the latch;
• in a delay mode, continuing to isolate the first and second latch power supply nodes from the respective first and second power supply potentials, while coupling a selected one of first and second memory bitlines to a respective one of the first and second signal nodes and providing a reference current to a selected one of the first and second signal nodes so as to develop a potential on the selected signal node corresponding to a state of a selected memory cell on the selected memory bitline;
• in a sense mode, coupling the first and second latch power supply nodes to the respective first and second power supply potentials such that the potential developed on the selected signal node causes the latch to assume a state corresponding to the state of the selected memory cell on the selected memory bitline;
• and
• in a read-out mode, coupling a read-out circuit to the first signal node or the second signal node so as to produce an output signal corresponding to the state of the latch.