Selection method of bit line redundancy repair and apparatus performing the same

A selection method of bit line redundancy repair, which is applied to a normal cell array having memory blocks and a redundancy cell array having redundancy blocks, comprising the steps of:

• providing a plurality of logical addresses of the memory blocks in the normal cell array;
• generating a plurality of extra fuse signals;
• generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, wherein the defective type is one of exactly two adjacent defective memory blocks, exactly three adjacent defective memory blocks, exactly four adjacent defective memory blocks and exactly two adjacent defective memory blocks plus another exactly two adjacent defective memory blocks;
• and
• selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code.

An apparatus performing bit line redundancy repair in a normal cell array having memory blocks and a redundancy cell array having redundancy blocks, the apparatus comprising:

• a redundancy repair enable circuit configured to generate a redundancy enable signal based on logical addresses of the memory blocks;
• means for configuring defective types of the memory blocks, wherein the defective types consist essentially of two adjacent defective memory blocks, three adjacent defective memory blocks, four adjacent defective memory blocks and two adjacent defective memory blocks plus another two adjacent defective memory blocks;
• means for sending a code matching one of the defective types;
• and
• a redundancy decoder circuit configured to receive the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with a plurality of redundancy blocks in the redundancy cell array.