Memory device having terminals for transferring multiple types of data
AssigneeMicron Technology, Inc.
InventorJoo S. Choi
Life of this patent
Estimating the term…
Abstract
A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.
Claims19
A method comprising:
- transferring a number of groups of data bits on a portion of a plurality of external terminals connected between a memory device and a controller;
- transferring a plurality of parity codes for the groups of data bits on the same portion of the plurality of external terminals, wherein transferring the groups of data bits occurs before transferring the parity codes;
- and
- comparing bits of the groups of data bits.
A method comprising:
- transferring a number of groups of data bits on a portion of a plurality of external terminals connected between a memory device and a controller;
- transferring a plurality of parity codes for the groups of data bits on the same portion of the plurality of external terminals, wherein the parity codes are transferred from the controller to the memory device;
- and
- comparing bits of the groups of data bits.
A method comprising:
- transferring data bits on lines of a memory device during a read operation;
- and
- transferring parity codes on the same lines used to transfer the data bits, wherein the parity codes are generated by the memory device, and wherein the data bits are transferred before the parity codes are transferred.
A method comprising:
- transferring data bits on lines of a memory device;
- transferring parity codes on the same lines used to transfer the data bits, wherein the parity codes are not generated by the memory device;
- and
- generating additional parity codes based on the data bits, wherein the additional parity codes are generated by the memory device.
Dependencies are inferred from the claim text.