Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

A method of programming selected ones of a plurality of memory segments in a memory array comprising a plurality of P-wells in a deep N-well within a P-type substrate, wherein each of the plurality of memory segments resides within a respective one of the plurality of P-wells, said method comprising of the steps of:

• setting the deep N-well to a positive voltage;
• setting the plurality of P-wells to a first negative voltage;
• setting a one of a plurality of word lines to the positive voltage;
• setting other ones of the plurality of word lines to a second negative voltage;
• setting at least one of a plurality of bit lines to the first negative voltage;
• setting other ones of the plurality of bit lines to substantially zero volts;
• setting a source select gate line to the first negative voltage;
• and
• setting a source select drain line to the first negative voltage,
• wherein the selected ones are programmed of the plurality of memory segments coupled to the one of the plurality of word lines and the at least one of the plurality of bit lines.