US 7,466,590 B2Granted

Self-boosting method for flash memory cells

AssigneeSanDisk Corporation

InventorsGerrit Jan Hemink, Hironobu Nakao, Shih-Chung Lee

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Abstract

A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled to the selected word line. Different intermediate boosting voltage(s) (e.g. of the order of five to ten volts) may be applied to one or more of the word lines adjacent to the selected word line (that is the word line programming the selected transistor), where the boosting voltage(s) applied to the word line(s) adjacent to the selected word line are/is different from that or those applied to other unselected word lines.

Claims37

Dependent claims

A method for programming a memory system, said system comprising strings of charge storage transistors for storing different charge states, each of said strings including two select transistors, each of said strings connected between one of a plurality of bit lines and a source line, said strings controlled by a common set of word lines, wherein a first charge storage transistor is in a first string of the strings and adjacent to one of the two select transistors in the first string, said method comprising:

applying a program voltage level through one of the word lines to a control gate that is capacitively coupled with a second charge storage transistor in a second string of the strings different from the first string to program the second transistor, said second transistor separated from the source line by three or more charge storage transistors in said second string when charge storage transistors closer to the source line than the bit line connected to the second string are programmed or separated from the bit line that is connected to the second string by three or more charge storage transistors in said second string when charge storage transistors closer to such bit line than the source line are programmed, said control gate controlling also to a third charge storage transistor in the first string;
coupling first voltage(s) to the first transistor and to one or more additional charge storage transistors that is or are different from the select transistors in the first string and adjacent to the first transistor;
turning off at least a fourth charge storage transistor in the first string between the source line and the third transistor, in order to electrically isolate the third transistor from transistors in the first string between the source line and the fourth transistor;
and
boosting, through some of the word lines, electrical potential(s) of channel regions of the first string of transistors by coupling boosting second voltage(s) to at least some of the remaining transistors in the first string, the second voltage(s) being higher than the first voltage(s), to boost said electrical potential(s) of channel regions of the first string of transistors to a value or values closer to the program voltage, thereby reducing program disturb.

2 more elements

A method for programming a memory system, said system comprising strings of charge storage transistors for storing different charge states, said strings including a first string, each of the strings including two select transistors, said strings controlled by a common set of word lines and connected between a plurality of bit lines and a source line, wherein a first charge storage transistor is in the first string and adjacent to one of the two select transistors, said method comprising:

applying a program voltage level to a first control gate that is capacitively coupled with a second charge storage transistor, and subsequently applying a program voltage level to a second control gate that is capacitively coupled with a third charge storage transistor different from the second transistor to program the second and third transistors, each of said second and third transistors being in a second string of the strings different from the first string and being separated from the source line by one or more charge storage transistors in said second string when charge storage transistors closer to the source line than the bit line connected to the second string are programmed or separated from the bit line that is connected to the second string by one or more charge storage transistors in said second string when charge storage transistors closer to such bit line than the source line are programmed;
and
coupling first voltage level(s) to the first transistor and to one or more additional charge storage transistors in the first string and adjacent to the first transistor;
and
boosting, through some of the word lines, electrical potential(s) of channel regions of the first string of transistors by coupling boosting second voltage level(s) to at least some of the remaining transistors in the first string, the second voltage level(s) being higher than the first voltage level(s), when a program voltage level is applied to the control gates coupled to the second and third transistors, to boost said electrical potential(s) of channel regions of the first string of transistors to a value or values closer to the program voltage, thereby reducing program disturb, wherein the first or second control gate also controls a fourth charge storage transistor in the first string, said method further comprising turning off at least a fifth charge storage transistor in the first string between the source line and the fourth transistor, in order to electrically isolate the fourth transistor from charge storage transistors in the first string between the source line and the fifth transistor.

2 more elements

A method for programming a memory system, said system comprising strings of charge storage transistors for storing different charge states, said strings including a first and a second string each connected between one of a plurality of bit lines and a source line and controlled by common word lines, each of said strings including a source select transistor connected to the source line, said method comprising:

applying a program voltage to a selected word line coupled to a selected charge storage transistor in the first string to program the selected transistor;
coupling by means of said common word lines first or second boosting voltages to at least some of the transistors in the second string to boost electrical potential(s) of channel regions of transistors in the second string to a value or values closer to the program voltage to reduce program disturb, wherein the first boosting voltage is coupled to a first charge storage transistor in the second string adjacent to the selected word line, and the second boosting voltage(s) is/are coupled to the remaining transistors in the second string except for the transistors coupled to the selected word line, the first boosting voltage being different from the second boosting voltage(s).

Dependencies are inferred from the claim text.

Facts

Application: 11/321,955Filed 28 Dec 2005 · continuation in part
Priority: 6 Feb 2004
Published: US 2006/0198195 A17 Sep 2006
Granted: 16 Dec 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/12
Programming or data input circuits: programming voltage switching circuits
G11C 16/3418
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: disturbance prevention or evaluation;…

Family

Application10/774,014Parent of this continuation-in-part · filed 6 Feb 2004
US 2006/0198195 A1Pre-grant publication · published 7 Sep 2006
US 7,161,833 B2Parent of this continuation-in-part
US 2005/0174852 A1Published application
US 7,466,590 B2This patent

From the US filing history. Foreign family members aren’t listed.

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