Voltage controlled static random access memory

A design structure instantiated in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a static random access memory (SRAM) that includes wordline circuitry and is powered by an SRAM voltage signal having a first voltage;
• and
• at least one wordline voltage regulator operatively configured to drive said wordline circuitry with a wordline voltage signal having a second voltage lower than the first voltage;
• wherein said SRAM is susceptible to read disturbances and said second voltage is selected so as to inhibit said read disturbances;
• and
• wherein said at least one voltage regulator includes a metastability voltage generator, and said SRAM includes a plurality of SRAM cells each having a pair of internal voltage nodes and said metastability voltage generator comprises one of said plurality of SRAM cells having said pair of internal voltage nodes electrically coupled to one another.