Level shifter circuit and method for controlling voltage levels of clock signal and inverted clock signal for driving gate lines of amorphous silicon gate-thin film transistor liquid crystal display

A method of controlling a voltage level of a clock signal of a gate driver for driving a liquid crystal display panel, comprising:

• receiving a clock activating signal and judging whether the clock-activating signal has a first level or a second level;
• judging whether a pre-charge clock-activating signal is activated when the clock-activating signal has the first level;
• increasing the voltage level of the clock signal from a negative external voltage level to a power supply voltage level when the pre-charge clock-activating signal is activated;
• increasing the voltage level of the clock signal from the power supply voltage level to a positive external voltage level when the pre-charge clock-activating signal is not activated;
• judging whether the pre-charge clock-activating signal is activated when the clock-activating signal has the second level;
• decreasing the voltage level of the clock signal from the positive external voltage level to a ground voltage level when the pre-charge clock activating signal is activated;
• and
• decreasing the voltage level of the clock signal from the ground voltage level to the negative external voltage level when the pre-charge clock-activating signal is not activated;

A method of controlling a voltage level of an inverted clock signal of a gate driver for driving a liquid crystal display panel, comprising:

• receiving an inverted clock activating signal and judging whether the inverted clock-activating signal has a first level or a second level;
• judging whether an inverted pre-charge clock-activating signal is activated when the inverted clock-activating signal has the first level;
• increasing the voltage level of the inverted clock signal from a negative external voltage level to a power supply voltage level when the inverted pre-charge clock-activating signal is activated;
• increasing the voltage level of the inverted clock signal from the power supply voltage level to a positive external voltage level when the inverted pre-charge clock-activating signal is not activated;
• judging whether the inverted pre-charge clock-activating signal is activated when the inverted clock-activating signal has the second level;
• decreasing the voltage level of the inverted clock signal from the positive external voltage level to a ground voltage level when the inverted pre-charge clock activating signal is activated;
• and
• decreasing the voltage level of the inverted clock signal from the ground voltage level to the negative external voltage level when the inverted pre-charge clock-activating signal is not activated.