US 7,466,191 B2 · Self reverse bias low-power high-performance storage circuitry and related methods

Abstract

An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

Claims9

Dependent claims

An integrated circuit comprising:

a bias voltage supply node;
a virtual ground node;
a first NMOS transistor including a first S/D electrically coupled to the virtual ground node and including a second S/D electrically coupled to the bias voltage supply node and including a gate electrically coupled to a first mode control node capable of receiving a voltage signal distinct from the virtual ground node;
and
a second NMOS transistor including a first S/D electrically coupled to the virtual ground node and including a second S/D electrically coupled to the first mode control node and including a gate electrically coupled to a second mode control node.

2 more elements

An integrated circuit driver circuit comprising:

a first bias voltage node;
a second bias voltage node;
a first mode control node;
a second mode control node;
and
an inverter circuit including a PMOS transistor and a first NMOS transistor,
wherein the inverter includes a data node comprising interconnected first source/drains (S/D) of the PMOS transistor and first NMOS transistor,
wherein the inverter includes an inverter control node electrically coupled to gates of the PMOS transistor and first NMOS transistor,
wherein a second S/D of the PMOS transistor is electrically coupled to the first bias node,
a second NMOS transistor including a first S/D electrically coupled to a second S/D of the first NMOS transistor and including a second S/D electrically coupled to the second bias node and including a gate electrically coupled to the first mode control node, and
a third NMOS transistor including a first S/D electrically coupled to the second S/D of the first NMOS transistor and including a second S/D electrically coupled to the first mode control node and including a gate electrically coupled to the second mode control node.

8 more elements

An integrated circuit driver circuit comprising:

a first bias voltage node electrically coupled to a first power supply level;
a second bias voltage node electrically coupled to a second power supply level lower than the first power supply level;
a first mode control node;
a second mode control node;
an address signal line;
a word line;
a virtual ground node;
an inverter circuit including a PMOS transistor with a first source/drain (S/D) electrically coupled to the word line and a first NMOS transistor with a first S/D coupled to the word line;
wherein gates of the PMOS transistor and first NMOS transistor are electrically coupled to the address signal line;
wherein a second S/D of the PMOS transistor is electrically coupled to the first bias voltage node;
wherein a second S/D of the first NMOS transistor is electrically coupled to the virtual ground node;
a second NMOS transistor including a first S/D electrically coupled to the virtual ground node and including a second S/D coupled to the second bias voltage node and including a gate coupled to the first mode control node;
and
a third NMOS transistor including a first S/D electrically coupled to the virtual ground node and including a second S/D electrically coupled to the first mode control node and including a gate electrically coupled to the second mode control node,
wherein the driver circuit is responsive to receiving, at the first mode control node and the second S/D of the third NMOS transistor, a voltage higher than the second power supply level, and at the second mode control node a voltage lower than the second power supply level by causing the driver to be in an active mode including that the second NMOS transistor is on and the third NMOS transistor is off,
wherein the driver circuit further is responsive to receiving, at both the first mode control node and the second S/D of the third NMOS transistor, a voltage lower than the second power supply level, and to receiving at the second mode control signal voltage higher than the voltage received at the first mode control node by causing the driver to be in a standby mode including that the second NMOS transistor is off and the third NMOS transistor is on.

13 more elements

Dependencies are inferred from the claim text.

Self reverse bias low-power high-performance storage circuitry and related methods

Life of this patent

Self reverse bias low-power high-performance storage circuitry and related methods

Life of this patent

Abstract

Claims9