US 7,466,175 B2 · Capacitance multiplier circuit

Abstract

An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Claims13

Dependent claims

An integrated circuit including a capacitance multiplier, comprising:

a reference capacitor coupled between a first node and a second node, wherein the reference capacitor has a reference capacitor current;
and
a current mirror arrangement coupled between the second node and a point of reference potential, wherein the current mirror arrangement includes
a first transistor Q1 having a first terminal coupled to the second node,
a second transistor Q2 having a first terminal coupled to the first node and
an operation amplifier coupled between the second node and a second terminal of the first transistor and the second transistor Q2 and the point of reference potential,
wherein the current mirror arrangement has a current gain factor N, and wherein the current mirror arrangement varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current.

4 more elements

An integrated circuit including a phase-locked loop (PLL) loop filter circuit, comprising:

a loop filter capacitor coupled between a first node and a first intermediate node;
a loop filter resistor coupled between the first node and the first intermediate node;
a capacitance multiplier coupled between the intermediate node and a point of reference potential,
wherein the capacitance multiplier includes
a reference capacitor coupled between the first intermediate node and a second intermediate node, wherein the reference capacitor has a reference capacitor current associated therewith, and
a current mirror arrangement coupled between the second intermediate node and the point of reference potential, wherein the current mirror arrangement includes
a first transistor Q1 having a first terminal coupled to the second intermediate node,
a second transistor Q2 having a first terminal coupled to the first intermediate node, and
an operation amplifier coupled between the second intermediate node and a second terminal of the first transistor and, the second transistor Q2 and the point of reference potential,
wherein the current mirror arrangement is configured in such a way that reduces the amount of parasitics within the capacitance multiplier.

7 more elements

Dependencies are inferred from the claim text.

Capacitance multiplier circuit

Life of this patent

Capacitance multiplier circuit

Life of this patent

Abstract

Claims13