Fast lock scheme for phase locked loops and delay locked loops

A method comprising:

• comparing a reference signal to a feedback signal to provide a first signal and a second signal indicative of the phase difference between the reference signal and the feedback signal, wherein the first signal and the second signal have pulses such that the first signal pulses have wider widths than that of the second signal pulses when the phase difference between the reference signal and the feedback signal has a first algebraic sign and the first signal pulses are less than the second signal pulses when the phase difference between the reference signal and the feedback signal has a second algebraic sign opposite to that of the first algebraic sign;
• providing a low impedance path from a node to a source having a reference voltage to charge or discharge a capacitor;
• receiving both the first and second signals after the reference and feedback signals are compared;
• detecting a phase transition based on the first and second signals;
• and
• removing the low impedance path when the phase transition in the first and second signals is detected, wherein the pulses of the first signal and the pulses of the second signal satisfy a first ordered relationship before the phase transition occurs and satisfies a second ordered relationship after the phase transition occurs.

A computer system comprising:

• a processor;
• memory;
• and
• a memory controller coupled to the processor to access the memory, the memory controller comprising:
• a phase detector to provide a first signal having pulses and a second signal having pulses, wherein the first and second signals are indicative of the phase difference between a reference signal and a feedback signal;
• a capacitor;
• a start-up circuit to charge or discharge the capacitor when enabled;
• and
• a phase transition detector to disable the start-up circuit in response to detecting a phase transition, wherein the phase transition detector is to receive both the first and second signals provided by the phase detector before the phase transition is detected, and wherein the pulses of the first signal are wider than the pulses of the second signal before the phase transition and are smaller than the pulses of the second signal after the phase transition.