Floating gate drive circuits

A floating gate drive circuit for a power switch having a source or reference terminal that swings between two non-zero dc voltages comprising,

• a gate buffer capable of providing sufficient voltage to fully enhance said power switch and sufficient current capability to fully charge and discharge a control terminal of said power,
• a source of gate timing information coupleable to said gate buffer,
• a source of dc gate drive voltage and energy,
• a rectifier having a first terminal connected to a first terminal of said source of dc gate drive voltage and energy,
• a first capacitor having a first terminal connected to a second terminal of said rectifier,
• a second capacitor having a first terminal coupleable to an output of said gate buffer and having a second terminal coupleable to said control terminal of said power switch,
• switch means having a control terminal coupleable to said source of gate timing information, a first main terminal connected a second terminal of said source of dc gate drive voltage and energy, and a second main terminal connected to a second terminal of said first capacitor,
• a third capacitor having a first terminal connected to said second main terminal of said switch means and having a second terminal connected to a reference terminal of said power switch,
• voltage clamping means having a first terminal connected to said control terminal of said power switch and having a second terminal connected to said reference terminal of said power switch,
• whereby said switch means and said rectifier enable charging of said first capacitor to a peak-to-peak voltage substantially equal to a voltage of said source of dc gate drive voltage and energy suitable for driving said power switch, and said switch means together with said voltage clamping means applies a voltage to said second and third capacitors whereby a suitable mechanism for controlling said power switch is achieved.