Look-up table structure with embedded carry logic
AssigneeTier Logic, Inc.
InventorRaminda Udaya Madurawe
Life of this patent
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Abstract
A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages; and the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure; and the third intermediate LUT stage generates a carry-out signal.
Claims20
A programmable multi input look up table (LUT) structure of an integrated circuit adapted to implement an arithmetic function, comprising:
- a configurable means of partitioning the LUT structure to a first, a second and a third intermediate LUT stage, each said LUT stage comprising a plurality of LUT value inputs, one or more inputs and an output;
- wherein the third intermediate LUT stage is further adapted to receive a carry-in signal as the LUT value input and the output of first intermediate LUT stage as an input to generate a carry-out signal as the output.
A programmable multi input look up table (LUT) structure of an integrated circuit adapted to implement an arithmetic function with two bits, a carry-in signal, a sum signal and a carry-out signal;
- comprising:
- a first intermediate LUT stage comprising:
- an output;
- and
- at least two inputs, each said input coupled to a said bit;
- and
- a plurality of LUT values, said LUT values configured to generate an exclusive OR function of the two inputs at said output;
- and
- a second intermediate LUT stage comprising:
- an output generating the sum signal;
- and
- a first input coupled to the carry-in signal and a second input coupled to the output of first intermediate LUT stage, and
- a plurality of LUT values, said LUT values configured to generate exclusive OR function of the two inputs at said output;
- and
- a third intermediate LUT stage comprising:
- a first LUT value input coupled to the carry-in signal, and a second LUT value input coupled to one of the two bits;
- and
- an input coupled to the output of first intermediate LUT stage;
- and
- an output that generates the carry-out signal.
A configurable look up table (LUT) structure of an integrated circuit comprising:
- a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein:
- the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages;
- and
- the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure;
- and
- the third intermediate LUT stage generates a carry-out signal.
Dependencies are inferred from the claim text.