System of digitally testing an analog driver circuit

A circuit, comprising:

• a control circuit configured to generate at least a first and second signal in response to a test enable signal;
• a differential driver circuit coupled to said control circuit, having a differential input node and a differential output node and configured to receive a differential input signal at said differential input node, amplify said differential input signal and transmit a differential output signal onto said differential output node in response said first signal;
• a programmable termination impedance circuit coupled to said control circuit and said differential output node, configured to generate a differential termination impedance at said differential output node in response to said second signal, said programmable termination impedance circuit comprises a plurality of resistor components, each resistor component having an associated switch for selectively connecting that resistor component from a voltage source to said differential output node, wherein at least one, but less than all of said resistor components are coupled to a first node of said differential output node and a remainder of said resistor components are coupled to a second node of said differential output node;
• and a differential receiver circuit coupled to said control circuit and said differential output node, configured to receive said differential output signal, convert said differential output signal to a single ended signal and transmit said single ended signal in response to said test enable signal.

A circuit, comprising:

• a control circuit configured to generate at least a first and second signal in response to a test enable signal;
• a differential driver circuit coupled to said control circuit, having a differential input node and a differential output node and configured to receive a differential input signal at said differential input node, amplify said differential input signal and transmit a differential output signal onto said differential output node in response said first signal;
• a programmable termination impedance circuit coupled to said control circuit and said differential output node, configured to generate a differential termination impedance at said differential output node in response to said second signal;
• and a differential receiver circuit coupled to said control circuit and said differential output node, configured to receive said differential output signal, convert said differential output signal to a single ended signal and transmit said single ended signal in response to said test enable signal, said differential receiver circuit comprising:
• a differential amplifier circuit coupled to said differential output node and configured to receive said differential output signal;
• a built-in offset voltage comparator circuit coupled to said differential amplifier circuit and configured to output a signal in response to said differential output signal and an offset voltage;
• an output stage coupled to said differential amplifier circuit and said built-in offset voltage comparator circuit and configured to transmit said single ended signal in response to said output signal of said built-in offset voltage comparator circuit;
• and a level shifter circuit coupled to said output stage and configured to transition power supply domains from an analog power supply domain to a digital power supply domain.